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But the decap shows that Panther Lake use HP cell for overall device, no HD cell. And I remember Panther Lake performance is not high ( its clock rate even lower than Arrow Lake), and it emphasizes more on efficiency. So question is why Panther Laker don not just use HD cell?
there could be any number of reasons.
they need the performance
The HP cell has better stability, lower error rate
The layout did not show a penalty for a larger cell. using a HD cell to save 1mm2 might not be a good idea. with chiplets and dummy silicon you could end up with no penalty.
I mentioned to someone on here that 20 years ago, we never used the most dense SRAM. Designers were not going to risk a product to save 2mm2.
there could be any number of reasons.
they need the performance
The HP cell has better stability, lower error rate
The layout did not show a penalty for a larger cell. using a HD cell to save 1mm2 might not be a good idea. with chiplets and dummy silicon you could end up with no penalty.
I mentioned to someone on here that 20 years ago, we never used the most dense SRAM. Designers were not going to risk a product to save 2mm2.
The reason for using HD cells is to increase density, and to reduce energy consumption per operation (gate transition) for cases where this matters more than maximum clock speed. For most CPUs HP cells are more appropriate, they're a better fit to the device priorities. For most ASICs HD cells are a better fit to the device priorities. Neither is "better" than the other, they have different pros and cons.
(but stability and error rate are nothing to do with it, at least not in any application I'm aware of...)
