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Nehalem was definitely a tock in the tick-tock model. I'm not sure about the internal core details (like OOO improvements or number of decoders, etc.), but Nehalem replaced FSB with QPI, which was a completely new cache coherent point to point interconnect architecture. So I think Nehalem was far beyond just Conroe+ with IMC.
Nehalem was definitely a tock in the tick-tock model. I'm not sure about the internal core details (like OOO improvements or number of decoders, etc.), but Nehalem replaced FSB with QPI, which was a completely new cache coherent point to point interconnect architecture. So I think Nehalem was far beyond just Conroe+ with IMC.
Thanks! I remember at Lockheed Martin, on the server side Nehalem was such an improvement it justified throwing 3 year old servers in the trash. Client was nor nearly as drastic but it was a good product.
On the Core 2 vs. IMC, A little funny now that chiplets have moved a bit backwards in terms of IMC integration. The IMC is a full die-hop away from the cores now. I definitely understand that's still a lot 'closer' (latency/bandwidth) than FSB, but it's definitely adding some latency, as we are seeing on certain workloads re: Raptor Lake vs. Arrow Lake.
I always wondered if how an IMC could have helped Pentium 4 vs. K8, probably still not enough..
Thanks! I remember at Lockheed Martin, on the server side Nehalem was such an improvement it justified throwing 3 year old servers in the trash. Client was nor nearly as drastic but it was a good product.
On the Core 2 vs. IMC, A little funny now that chiplets have moved a bit backwards in terms of IMC integration. The IMC is a full die-hop away from the cores now. I definitely understand that's still a lot 'closer' (latency/bandwidth) than FSB, but it's definitely adding some latency, as we are seeing on certain workloads re: Raptor Lake vs. Arrow Lake.
Totally agree. Chiplets, excuse me, tiles in Intel-speak, are a big redesign problem. That's why the Intel CPU design teams avoided them as long as possible, so long as manufacturing said they could name that tune on one big die. Nothing beats being on-die, performance or efficiency wise.
The big problem with FSB is that it was a bus. Worse yet, an inter-chip bus on a board. A bus is a shared medium, so all of the end stations on the bus must have exclusive access to send a message, and every send is essentially a broadcast to all end stations, so each station has to listen to every message to pick theirs' out of the total traffic flow. The technical term for a design like FSB is YUCK.
I assume MLID is correct on the skus. My understanding is that the 18A decisions on Nova Lake are related to capacity and cost of capacity. The problem with no foundry customers is that there is little flexibility now and no back up plans if product timelines change. you have to fill a fab or it falls apart. TSMC can provide that flexibility where Intel needs to build new fabs.
18A latest rumors: technology works well. yields have a plan. cost is affected by low volume and ramp in Fab 52 (so costs are higher than plan which will impact roadmap decisions).
I am a manufacturing guy with 20 years experience in advanced manufacturing.
I am looking at back side power delivery from a manufacturing standpoint.... to me it looks like a genius design from a product standpoint, but a huge challenge to manufacture, since you basically have to shave off the back of the die at micron accuracy, and then align the interconnect at sub micron accuracy, and it still has to happen at a reasonably high throughput. The cherry on top is this all has to be done with incredibly fragile workpieces where the slightest bit of contamination will ruin the die.
Manufacturing problems with this many layers of complexity often take many many years to work out.
I agree about BSPD. Intel should have offered two versions of next gen nodes like TSMC. 20A could have been offered like TSMC's N2 with no BSPD. While 18A could have been with BSPD. 20A could have been delivered more quickly and Intel would have bought more time to release 18A w/ BSPD.
If capacity is limited, should Intel reserve the 18A capacity for high-margin products like CWF, Diamond Rapids, and Jaguar Shores, while leaving desktop PC products to TSM? My understanding is that desktop PC products—despite crying the loudest—have relatively low margins. In my opinion, they are mainly for mindshare purposes.
I agree about BSPD. Intel should have offered two versions of next gen nodes like TSMC. 20A could have been offered like TSMC's N2 with no BSPD. While 18A could have been with BSPD. 20A could have been delivered more quickly and Intel would have bought more time to release 18A w/ BSPD.
But I don't think it's impossible to remove the BSPDN.
In Intel's development regime, the BSPDN development team was separate from the mainstream process development team, and it must have been a combination of these.
I assume MLID is correct on the skus. My understanding is that the 18A decisions on Nova Lake are related to capacity and cost of capacity. The problem with no foundry customers is that there is little flexibility now and no back up plans if product timelines change. you have to fill a fab or it falls apart. TSMC can provide that flexibility where Intel needs to build new fabs.
18A latest rumors: technology works well. yields have a plan. cost is affected by low volume and ramp in Fab 52 (so costs are higher than plan which will impact roadmap decisions).
In the first place, no matter how small it is, it is not possible to use all 18A manufacturing lanes for its own products because there are external customers.
If capacity is limited, should Intel reserve the 18A capacity for high-margin products like CWF, Diamond Rapids, and Jaguar Shores, while leaving desktop PC products to TSM? My understanding is that desktop PC products—despite crying the loudest—have relatively low margins. In my opinion, they are mainly for mindshare purposes.
18A latest rumors: technology works well. yields have a plan. cost is affected by low volume and ramp in Fab 52 (so costs are higher than plan which will impact roadmap decisions).
They need to show this in public PR to get any sort of customers they are hammering themselves due to all the rumors and negative pr Intel is getting latel. There ain't no way some customer would jump ship seeing this much negativity.
Well. I am more interested if these rumors are actually real rumors. I read that MLID often delete videos or tweets when he had been proven wrong. So I wonder are there any other ppl who confirm this rumor other than MLID.
Well. I am more interested if these rumors are actually real rumors. I read that MLID often delete videos or tweets when he had been proven wrong. So I wonder are there any other ppl who confirm this rumor other than MLID.
