Not a religious war, I'm not biased towards or against any foundry (and have been involved in process/foundry selection) -- but just a couple of points need making...
"10 customer 16nm tapeouts in 2014 so far" -- so maybe 5 customers have actually got 16FF silicon in their hands right now (see below)...
"TSMC is already in production with a 16nm FinFET network processor for HiSilicon" -- they've just delivered first samples, this is not "in production"
"Most of these people already have 16nm silicon" -- if 5=most (see above) it must be a pretty small event then, presumably only 7 or 8 companies attending?
"no fooling them with ambiguous slides and double speak" -- I know at least one of said companies is unhappy with 16FF not delivering claimed power savings -- so were they fooled?
From the TSMC OIP website: "With this forum, TSMC offers you an effective marketing venue..."
In other words, it's a marketing event for TSMC to promote their technology, and ecosystem (IP/software) partners to market their products to current and potential customers. Absolutely nothing wrong with that -- TSMC is a fantastic foundry with massive support -- but don't expect to see any shadow of doubt about how wonderful the technology and the ecosystem are and that all the problems are solved. I'm equally sure that if you went here:
GLOBALFOUNDRIES to Host Inaugural Global Technology Conference
you'd see exactly the same kind of presentations but with TSMC replaced by Globalfoundries, and everything being similarly wonderful. Nobody should be under any illusion that marketing events like these are in any way impartial, just put on the free rose-tinted glasses when you walk through the door.
As you say, your *opinion*... ;-)
Clearly your problem is with me personally, you made that evident by your first comments and this post is a byproduct of that.
For the record, test chips qualify as 16nm silicon in my definition and MANY people including EDA, IP, and early access fabless companies have 16nm Silicon. According to my notes more than 40 EDA tools and 700 IP have been qualified for 16nm. Do you have any idea how many test chips that required? You should also look at the agenda for OIP as it has 16nm silicon written all over it:
TSMC 2014 - Attendee Registration
I attend dozens of these conferences every year (including ISSCC and IEDM), I even help organize conference sessions. Last year I did a full day on FinFETs at EDPS and next year I'm doing a session on FinFET versus FD-SOI design challenges. I work inside the fabless semiconductor ecosystem by day and write about it extensively at night. I'm one of the last people that TSMC or anyone else for that matter should hand a pair of rose colored glasses to.