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Looking at [1], the ioff of 22nm finfet if 15pa/um , which i believe is the area of 130nm used for low power microcontrollers. Considering that the area of a 22nm implemented mcu would be far lower, there's a potential for creating a really great ,low power mcu.
And as far as i know this ioff number is far better than fdsoi.
I understand that what stands against this is the need of 22nm flash, analog IP, minimal die size due to IO pads.
I think that terepac ,with their unique packaging technology,which allows for packaging of tiny chips(maybe hundreds of um2).
Do you think the other issues are solvable ? is there work being done on them ? is the concept correct ?
Just to clarify, that level of Ioff was at a gate pitch of 108nm (20% more than the nominal pitch) to allow a significantly longer gate length than nominal. You can do that in any technology if you are not concerned about area penalty.
BTW, many interesting applications require some always on circuits. There you need capability to lower active power. Only for circuits that are sleep most of the time you want really low Ioff, and there a simpler way is just to turn the circuit off.
Khaki, do you mean that if we take for example 40nm , increase the gate size by something like 20% we'll get similar ioff ? Because i though low current in general has something to do with finfet.
Also it true that dynamic power is important ,but 22nm is much better at that than 130nm, without a doubt.
Hi, assuming just compare 22nm fin vs 130nm planer, you are absolutely right that 22 got dynamic power advantage. However you probably need better reliability for your micro controler.
130 chip might be bigger but your esd is robust, you don't care nbti, hci is a concern, but fin situation will be tougher. Tech node scaling does not move all the products to the smaller ones.
180,150,130 still got big market share for reliability concerns in my opinion, whereas 65/45 maybe favored by rf. 28 is strong hold for last planer node...
Fdsoi got interesting esd innovation,..
Khaki, do you mean that if we take for example 40nm , increase the gate size by something like 20% we'll get similar ioff ? Because i though low current in general has something to do with finfet.
Also it true that dynamic power is important ,but 22nm is much better at that than 130nm, without a doubt.
To be clear that particular transistor is roughly 50% longer than nominal not 20%. It needs 20% longer pitch. If very low Ioff is all you care, that can be done reasonably in any technology. Tens of pA is easy to do. Embedded DRAM - which is implemented in logic nodes - has even lower leakage spec.
Yes, you are right about active power being significantly lower in advanced nodes compared to 130nm. That's why many IoT applications - where you need to actually do something as opposed to a chip that sits there idle - are looking at advanced nodes. That's exactly why TSMC is doing 28ULP and Samsung is doing 28FD. 22nm FinFET would be an interesting competition to these two, and has relatively same density.
One big problem with using 22nm (or smaller) for microcontrollers is design/mask NRE cost. Usually an MCU portfolio consists of a large family of variants each optimised for a particular application with varying CPU capability, RAM/ROM size, peripherals, I/O, drivers etc. For this to work commercially the NRE cost of doing a new variant has to be relatively low, which immediately excludes anything smaller than 28nm -- or even 28nm for many applications, the NRE is still too high.
This is apart from the technical issues such as flash availability, embedded DRAM, high-voltage I/O drivers and so on.
One big problem with using 22nm (or smaller) for microcontrollers is design/mask NRE cost. Usually an MCU portfolio consists of a large family of variants each optimised for a particular application
Actually in most product ranges there are only a few different die designs, with the peripheral selection being done by pad wiring. And of course the experts at this are Intel who now seem to manage to get 100s of variants from just a few die designs.
But I don't think 22nm is that relevant to MCUs as it will probably be pad limited unless you need vast amounts of flash.
Actually in most product ranges there are only a few different die designs, with the peripheral selection being done by pad wiring. And of course the experts at this are Intel who now seem to manage to get 100s of variants from just a few die designs.
But I don't think 22nm is that relevant to MCUs as it will probably be pad limited unless you need vast amounts of flash.
The number of MCU die designs depends on the strategy a company uses to address multiple markets; in the ones I've seen from the inside, unit cost was so critical that it was always better to do multiple carefully-optimised variants than a fused/programmed bigger die. Of course this tradeoff would change if the NRE went through the roof with 22nm, but then the unit cost would go up...
Whether MCUs are pad limited depends on the target market (low-end small, high-end big) and number of peripherals needed, many that I saw were core-limited. But I do agree that MCUs are a case where an advanced (expensive) process like 22nm makes little sense -- and these processes tend not to have integrated flash available anyway.
The number of MCU die designs depends on the strategy a company uses to address multiple markets; in the ones I've seen from the inside, unit cost was so critical that it was always better to do multiple carefully-optimised variants than a fused/programmed bigger die.
Obviously depends on the company and process, but STM for instance offer 1000s of cores but if you poke inside them for 'unimplemented peripherals' or open the package you can see they use the same die for quite a few products.
Obviously depends on the company and process, but STM for instance offer 1000s of cores but if you poke inside them for 'unimplemented peripherals' or open the package you can see they use the same die for quite a few products.
This is all a matter of degree -- not every single product will have its own die (because there would be thousands!), but still there are always families of dies needed to cover the required range, each of which then appears as multiple products depending on fusing/package/bonding etc.
The optimum number of different die depends on the unit cost/NRE tradeoff, but there will always be several needed in an MCU family -- and this number would be much fewer for 22nm, which means more wasted silicon on more sub-optimum family members.
