Layout - Angles in routing for sub-50nm process nodes ...

[harpoon]

As process geometries continue to shrink, should fabs be relaxing the rules on orthogonal routing and orthogonal vias ? As far as I can tell, there are 3 areas of concern/change :-
a) Fabs - The need to ensure mask making tools/algorithms lend themselves to 45 degree polygons (including vias). Incrementally, they can introduce 15, 30, 60 and 75 degree routing rules. There is also the issue of "off-grid" vertices that need to be addressed. Will GDS be the preferred format for these type of layouts ? Will vias be allowed to be "diamond" shaped ? (if you look at what is manufactured, they are more like circles than squares).
b) Layout capture - In addition to DRC verification, how would new tools handle the new shapes ? Automatic path generators are notorious for changing path widths when routed at 45 degree angles just to be on-grid. I think most layout tools already allow non-orthogonal routing, with some better than others at handling it.
c) P+R tools for digital design - Will this extra degree of freedom allow for "better" routing (maybe not as dense) ? It will definitely increase the complexity of the routing algorithm ... maybe exponentially. However, it may help for very high speed designs and when timing closure is critical. Maybe something for the future ? Or is this a non-starter ?

Ultimately, it needs to be driven by whether there is a performance improvement I guess ...



Comments anyone ?

 

[Daniel Payne]

Back in the day we used 45 degree routing inside DRAM cells all the time, however because of DFM and Litho concerns I don't see all-angle IC layout returning any time soon.

 

[Staf_Verhaegen]

X Initiative (RIP?)

c) P+R tools for digital design - Will this extra degree of freedom allow for "better" routing (maybe not as dense) ? It will definitely increase the complexity of the routing algorithm ... maybe exponentially. However, it may help for very high speed designs and when timing closure is critical. Maybe something for the future ? Or is this a non-starter ?

For 90 and 65nm there has been an X initiative (see for example UMC Announces Readiness for 65-nanometer X Architecture Designs) where 45deg routing was allowed. They claimed it would allow much efficienter chips. Last information I could find is 2006 though and the website at xinitiative.org seems to be gone. The website still seem to be registered by Cadence though.
Adding even more flexibel routing (30deg, 22.5deg) would increase mask and litho complexity too much with very limited improvement.

greets,
Staf.

 

[harpoon]

If we just stick to 45 degree routing, would the masks be more difficult to make ? I am guessing not as it is already allowed in analogue layouts. What I would like to know if the big digital P+R EDA vendors have tried 45 degree routing ? I am guessing if vias can done as diamond shapes, then 45 degree routing would definitely make sense as metal wires can just end as 45 degree polygons with a diamond via at the end.

I am intrigued by this "X Architecture Design" ... maybe 45 degrees have been tried and failed to work ? Does anyone know ?

 

[Beth Martin]

I worked in the X Architecture group at Cadence. The engineers on the project all came from the Simplex acquisition in 2002. It was headed up by Aki Fujimura (now the CEO of D2S). We had a pretty complete P&R flow, including FP, placement, routing, extraction, timing and opt. We also had some tapeouts (including a giant ATI chip), so somewhere out there are some chips with diagonal routing.
Here's a press release about it -- ATI produces first X architecture chip, says Cadence
However, there are no libraries of standard cells and vias to complement an octagonal layout world. Fabrication needed nothing special to make the diagonal lines, so I imagine making diamond/octagonal vias would also be possible with no process modifications. The technology was good for saving WL for some designs. All other things equal, I would see 3-15% lower WL and via count between Manattan and X routing. I don't recall all the factors that went into killing the X Architecture project.

 

[Kiby]

We looked at X years ago when it was Simplex. I knew it would die under Cadence. It was being sold to us as a service not a tool sale. Then Cadence said it would be tools but we never saw anything even though they bragged about tape outs. Diagonal routing makes sense from a design level but manufacturing is another story. Even more so now with RDRs coming at us at 28nm. My guess is that the foundries killed X due to yield.

Kiby!

 

[Beth Martin]

New technology like X Architecture is often offered as a design service because the tool stability (and usability) isn't up to snuff. Even after is was stable enough to release, it still required a lot of support. The engineering and support group was small, so like any startup, we had to screen potential customers. So, if a design wasn't in the sweet spot, we wouldn't waste everyone's time trying to force diagonal routes onto it.

I'm pretty certain that X Architecture wasn't killed by the foundries, or by technical infeasibility. TSMC had no problem developing a few extra rules for it. I believe it died due to simple business calculations ($engineering - $revenue = layoffs), and reluctance of the IC 'ecosystem' to adopt the new style. It was better for some designs, but not enough better for all designs to warrant the extra effort.

Another interesting note is that Cadence attempted a revenue sharing model with X Architecture. Something along the lines of "we guarantee to save you $xx, you pay us yy% of your savings." Turns out that no customer would sign on to that, partly because it changes which corporate budget the money comes from, partly because semi companies don't want to open the door to 'reach through' or revenue sharing to tool suppliers. They like the standard, predictable two year license fee.

 

[harpoon]

Reading all the posts so far, it seems that the X architecture is a good idea technically and the only problem is finding a revenue stream ? Is this a fair comment ?

I don't really see any yield issues here ... afterall when it comes out on silicon, vias are not really squares are they.

With the shrinking of device features, will it make a comeback, i.e. be mandatory for really high performance designs at 28nm ?

And will Synopsys take it further ? It seems to make sense for them since they have the tools and can probably leverage it for their IPs and designs.

 

[Daniel Payne]

What I read about 28nm and 20nm nodes it appears that 1D layout (M1 lines only one direction, M2 lines only one direction, etc.) like that proposed by Tela is going to be the norm, which means little hope for the X architecture and diagonal routing.

 

[harpoon]

Interesting. If you look at the Tela data, it appears that the maximum clock frequency has gone down ! This is consistent with what has been discussed so far. For performance, diagonal or unrestricted routing is the best.

However, it cannot be denied that the standard cells are a lot smaller ... which directly translates to cost saving !

so we not see this in the mainstream ... but maybe Intel is interested ? They have hit a brickwall in terms of processor speed in recent years !

 

[Beth Martin]

The X Architecture only used diagonal routing on higher metal layers. So, if preferred direction on M1 was horizontal, M2 vertical, M3 horizontal, M4 45-diag, M5 135-diag, M6 45, M7 135, etc. Allowing free, any-direction routing on all layers is a bad idea. The benefit of diag routing on higher layers is to reduce the number of vias and jogs needed to get a long route done, and it seems that this would only get more important at smaller process nodes. Plus, it makes for very pretty layouts.

 

[harpoon]

my thoughts exactly ... smaller process nodes might bring about a revival in X Architecture ... and even diagonal/octagonal vias !

 

[Staf_Verhaegen]

and even diagonal/octagonal vias !

Vias on wafer are circles anyway. So how they are drawn in layout is determined by the limitations of the EDA tools and also the OPC software.

greets,
Staf.

 

[Brad Falch]

What I read about 28nm and 20nm nodes it appears that 1D layout (M1 lines only one direction, M2 lines only one direction, etc.) like that proposed by Tela is going to be the norm, which means little hope for the X architecture and diagonal routing.

As Daniel said, the limitations are primarily in manufacture. It's not so much in "mask making" as it is in the actual pattern-transfer process on a scanner in the fab.

With the illumination styles needed to print these small features, it becomes very difficult to support all 4 directions (horizontal, vertical, pos-45 and neg-45) at the same time. So, we've eliminated two of them to get higher resolution by limiting to horizontal and vertical. It's possible to get similar resolution by limiting to the two 45-degree directions, too, but I think the design software infrastructure isn't built to support that.

And, as Daniel points out, the latest resolution enhancements are forcing us to limit to one direction only. That could be at the design stage, or decomposing a two-direction layout as a post-process.

-Brad