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Japan's Rapidus beckons global semiconductor talents, TSMC must prevent brain drain

Daniel Nenni

Daniel Nenni

Admin
Staff member
Japan's Rapidus beckons global semiconductor talents, TSMC must prevent brain drain

Reuters reports that in order to master 2-nanometer technology, Japanese semiconductor startup Rapidus plans to launch a recruitment plan to absorb global semiconductor talents in order to revive Japan's chip industry.

Rapidus plans to start mass production of 2nm in Japan in 2027. It is actively cooperating with IBM and Imec, and is also actively recruiting talents. It recruits industry veterans domestically and seeks professional talents abroad. Tetsuro Higashi, the 74-year-old person in charge, said that talent recruitment is not limited to Japan, but will expand to the world and actively attract talents.

Rapidus has about 250 employees as of this month, some interning at IBM's semiconductor labs in upstate New York. TSMC and Samsung have mass-produced 3 nanometers and will mass-produce 2 nanometers in 2025. Japan's latest semiconductor production line is still stuck at 40 nanometers.

In addition to actively planning for 2nm mass production, Rapidus is collaborating with the University of Tokyo and the French semiconductor research institute Leti to jointly develop the basis for semiconductor design with a circuit line width of 1nm. The two parties will begin personnel exchanges and technology sharing from 2024. French research institution Leti will contribute its chip component expertise to build 1-nanometer process infrastructure.

Market participants said Rapidus's plan to recruit semiconductor talents globally shows that Japan is short of cutting-edge semiconductor talents. TSMC's Kumamoto plant is nearing completion and is considering building a second plant, and even has plans for a third plant. This means that TSMC also needs to send manpower to Japan. These people may also be Rapidus's targets. TSMC has to pay attention while expanding its overseas production. Brain drain problem.

日本 Rapidus 向全球半導體人才招手，台積電須防人才外流問題

路透社報導，日本半導體新創企業 Rapidus 為了掌握 2 奈米技術，計劃開啟招兵買馬計畫，吸納全球半導體人才，以重振日本晶片業。 Rapidus 計劃 2027 年日本開始大規模生產 2 奈米，積極和 IBM 和 Imec 合作，也積極徵才，國內招募產業資深人士，國外尋求專業人才。74 歲負責人...
finance-technews-tw.translate.goog finance-technews-tw.translate.goog
 
Fred Chen said:
IBM had developed nanosheet as early as 5nm (with Samsung and Globalfoundries), so they could extend it to 2nm;
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Is see no reason why they wouldn’t do a 2”nm” HNS given everyone else is.
Fred Chen said:
the VTFET is also from working with Samsung.
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I know they said it was a possible option post 2nm, but I haven’t seen Samsung really talk much about it besides that. As for the current fab IBM is doing their VTFET research, I thought those wafers were coming out of Albany Nanotech?
Fred Chen said:
It's an interesting post-nanosheet alternative to CFET.
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Agreed, I think they are nifty. With that said, the challenges of interconnect scaling make it seem like a worse solution than CFET and not a whole world of difference better than HNS. I think there is a strong angle for trying to make a VTFET node as an SRAM only node. Interconnects are less of a concern given the array nature of SRAM and lower power delivery requirements of HDCs. Bonus points because until we get to monolithic 3D, it seems like N3 will not be the only node where SRAM cost per bit increases node over node.
Fred Chen said:
The trouble with nanosheet is they do not offer scaling of CGP.
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I don’t understand this to be true Fred. The better electrostatics should enable a poly shrink. Admittedly the electrostatic improvement is smaller than the jump from planar to finFET, and the theoretical maximum pp reduction will be smaller than what we were able to squeeze out of finFETs. Of course that is only one half of the equation, the other is the challenge of poly patterning.
 
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It's actually IBM themselves who said nanosheets, while offering better gate control, still could not scale CGP beyond ~40 nm. https://www.allaboutcircuits.com/ne...m-researchers-who-built-new-vtfet-transistor/
While you can say nanosheet offers a narrow range of scaling, maybe from ~50 nm to ~40 nm, yet still 45 nm CGP FinFETs were already shown by TSMC at IEDM 2022.

VTFET like CFET needs to benefit from buried contacts. It could still be lower transistor density than CFET, unless they somehow stack NFET on PFET or PFET on NFET, but more limiting would be the number of channels per transistor.
 
So they have 250 people and they are partnering with IBM and IMEC? and they will have mass production in 2027? Who is building the fab (I assume basebuild is done?)
 
Fred Chen said:
IBM had developed nanosheet as early as 5nm (with Samsung and Globalfoundries), so they could extend it to 2nm; the VTFET is also from working with Samsung. It's an interesting post-nanosheet alternative to CFET. The trouble with nanosheet is they do not offer scaling of CGP.
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To me IBM 2nm is still a step ahead of the commercial NS processes shown so far, since it has the isolation layer under the bottom gate.
 
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So when they say talent, does this mean Process / Materials / Chemical engineers Or
Does this also include design engineers?
 
Dick James said:
To me IBM 2nm is still a step ahead of the commercial NS processes shown so far, since it has the isolation layer under the bottom gate.
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I am wondering how IBM brings its semiconductor research and breakthroughs into high volume commercial production. In the past many years IBM had announced several industry's firsts but it seems most of them are limited or used only by IBM on its mainframes and Aix products. Samsung foundry is probably the only leading edge foundry uses IBM's technologies but Samsung is struggling.

Is it because IBM's advanced technologies still too far from commercialization?
 
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MKWVentures said:
Side note: Since TSMC N2 is not 2nm anywhere and Intel 20A is not 2nm anywhere (neither company claims 2nm)... is this technology actually 2nm somewhere? @Daniel Nenni
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The nm identifier was based on gate length down to 28nm. FinFETs changed that to a marketing term which is no longer based on actual measurements. TSMC added the Nx term at 7nm but they still say nm on their website so it is a transition in process. Intel is using 20a and TSMC is using N2 but Samsung uses 2nm. it is just a marketing/branding competition now.
 
Daniel Nenni said:
The nm identifier was based on gate length down to 28nm. FinFETs changed that to a marketing term which is no longer based on actual measurements. TSMC added the Nx term at 7nm but they still say nm on their website so it is a transition in process. Intel is using 20a and TSMC is using N2 but Samsung uses 2nm. it is just a marketing/branding competition now.
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I didnt know Samsung still used 2nm... good info. I talked to Intel and TSMC and both said that it was very intentional not to use "nm" since it is clearly and well documented to be false.
 
Daniel Nenni said:
The nm identifier was based on gate length down to 28nm. FinFETs changed that to a marketing term which is no longer based on actual measurements.
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I have heard from multiple old timers that the "nm" numbers after 130nm were totally divorced from gate length. It makes sense why that is the case too. That was where Dennard scaling broke down and we couldn't just keep linearly shrinking the gate length for the same MOSFET by 0.7x every node unless we wanted the leakage current to equal to active current. Although if we really want to be extra pedantic we could say that 65"nm" was a 5 atom node (which is like 1 or 2nm is memory serves) because that is how thin those gate oxides were before HKMG allowed the oxide thickness to go WAY up.
 
Paul2 said:
Any VTFET is very easy to turn into a CFET, it's naturally more easier to do with a vertical transistor.
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How is that? vertically aligned CFET starts from alternating epitaxial layers on the featureless wafer just like nanoribbons, and then uses clever etching to form different N and P effects at different depth. At least that is the plan as revealed by IMEC and others.

This is how they get the high crystal quality over multiple layers - form it on uniform epitaxy before there are any devices that restrict the use of annealing temperatures. Why does VFET make vertical differentiation easier?
 
Tanj said:
How is that?
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Start on SOI wafer, mask NMOS channel, P dope, deep etch to form channels, deposit insulator, deposit common gate, etch gate, etch hole for the drain contact, deposit backend.

Tanj said:
Why does VFET make vertical differentiation easier?
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Because vertical differentiation becomes horizontal differentiation.

However, stacked common channel structure VTFET would be a different story indeed.
 
Paul2 said:
Because vertical differentiation becomes horizontal differentiation.
However, stacked common channel structure VTFET would be a different story indeed.
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How would VTFET compete with CFET if it is not yet stacked? I could understand if VTFET is on track to be in the market earlier than CFET, but that does not seem to be happening. So VTFET seems likely to need vertical pairing from the start if it is to be mainstream competition.

Also, common channel seems limited utility. Key standard cells use separate N and P channels more often than common.
 
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