CALL FOR POSTERS AND PARTICIPATION:
International Workshop on Heterogeneous Computing Platforms (HCP)
November 6, 2014
Hilton San Jose, CA
Registration through ICCAD
After the end of Dennard scaling, power has become the limiting factor for modern designs. In the last decade, the computing industry relied on multiprocessors to achieve higher performance while satisfying system power constraints. Due to difficulties in task-level parallelism, however, the expected performance gain with increasing core counts is limited. As an alternative, heterogeneous compute resources can be utilized to achieve higher performance and better energy efficiency. Heterogeneous computing is becoming the norm for different platforms, including servers and mobile devices. General purpose CPUs can be paired up with additional processing units such as vector units (SSE/AVX), GPUs, FPGAs, and custom accelerators. The rapid growth in this field however, poses a broad range of new challenges in multiple areas such as programming, synthesis and implementation of applications. Solving these open problems requires interdisciplinary collaboration involving various research communities. This workshop will provide an open forum for discussions and exchange of ideas on these topics.
Key Topics
- Architectural trends and challenges for heterogeneous platforms integrating CPUs, GPUs, DSPs, FPGAs, and other custom hardware.
- Emerging applications well-suited for heterogeneous computing platforms, success stories and works in progress.
- Heterogeneous programming models and related topics such as cache coherency, data allocation, task allocation, and parallelization.
- Computer-Aided Design (CAD) for heterogeneous computing platforms, including but not limited to source-level transformations, hardware/software partitioning, architecture exploration, high level synthesis, power/performance estimations, and other implementation issues.
Poster Submission Instructions:
To present a poster at the workshop, please submit an abstract to EasyChair.
Your submission must include the following information: (1) poster title, (2) author names and affiliations, (3) abstract (up to one page). To be considered in the review process, your abstract must be submitted by September 8, 2014. Notification of acceptance will be sent to you on September 15, 2010.
Important Dates:
Submission deadline for poster abstracts: September 8, 2014
Notification of acceptance: September 15, 2014
Early registration deadline: October 6, 2014
Workshop: November 6, 2014
Other Information:
Please visit the ICCAD web site for other important information on technical program, online registration, hotel, travel, etc. For any questions, please contact the organizers:
Gi-Joon Nam or Mustafa Ozdal
(Tentative) Workshop Program
08:15 - 08:30 Opening Remarks
08:30 - 10:30 Emerging Heterogeneous Architectures
- "ASPIRE: Specializing the Software and Hardware Stacks”, Krste Asanovic, University of California, Berkeley
- “Acceleration-Rich Architectures - from Single-chip to Datacenters”, Jason Cong, University of California at Los Angeles
- “Architecting and Exploiting Asymmetry in Multi-Core Architectures”, Onur Mutlu, Carnegie Mellon University
10:30 - 11:00 Break
11:00 - 12:00 High-Level Synthesis and Applications on Heterogeneous Platforms
- “FCUDA: the CUDA to FPGA Compiler”, Deming Chen, the University of Illinois at Urbana-Champaign
- “Towards Efficient Next-Generation Genome Sequencing”, Mishali Naik and Ganapati Srinivasa, Intel
13:00 - 15:00 Latest Heterogeneous Platforms and Programming Models
- “Bringing Shared-Memory Reconfigurable Logic to the Datacenter and the Cloud”, Peter Hofstee, IBM Austin Research Lab
- “Title TBD: Intel Xeon Phi architecture”, Robert Geva, Intel
- “OpenCL on FPGAs: Custom Data Paths for Energy Efficient Computation”, Deshanand Singh, Altera
15:30 - 17:00 Applications on Heterogeneous Platforms II
- “Key-Value Store Acceleration with OpenPower”, Michaela Blott, Xilinx
- “Text-Analytics Acceleration work with P8/CAPI/FPGA”, Christoph Hagleitner, IBM Zurich Research Laboratory
- “Title TBD: Monte Carlo Simulation Acceleration with P8/FPGA”, Shakti Kapoor, IBM Server & WS Division
<script src="//platform.linkedin.com/in.js" type="text/javascript">
lang: en_US
</script>
<script type="IN/Share" data-counter="right"></script>