
Intel Shows Off Intel 3, 20A, 18A, Glass & Quantum Wafers at the Innovation Event
At the Innovation Event, Pat Gelsinger displayed quite a lot of wafers based on Intel's upcoming process nodes and designs.

Intel 18A wafer shown:
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Are they?In the process section intel prettied up their VLSI graphs. Besides the eye candy the more interesting thing is that MTL yields are better than at the Skylake or Tigerlake launches on the fixed 14nm and 10nm SF nodes respectively.![]()
Intel Details Core Ultra ‘Meteor Lake’ Architecture, Launches December 14
The Intel 4 process node has Intel’s highest Day-Zero yields in a decade.www.tomshardware.com
That's the idea behind chiplets though right? Smaller dies = higher yields.In the process section intel prettied up their VLSI graphs. Besides the eye candy the more interesting thing is that MTL yields are better than at the Skylake or Tigerlake launches on the fixed 14nm and 10nm SF nodes respectively.![]()
Intel Details Core Ultra ‘Meteor Lake’ Architecture, Launches December 14
The Intel 4 process node has Intel’s highest Day-Zero yields in a decade.www.tomshardware.com
That's a pretty low bar though. Intel had yield problems on launch day with both 14nm and 10nm.In the process section intel prettied up their VLSI graphs. Besides the eye candy the more interesting thing is that MTL yields are better than at the Skylake or Tigerlake launches on the fixed 14nm and 10nm SF nodes respectively.![]()
Intel Details Core Ultra ‘Meteor Lake’ Architecture, Launches December 14
The Intel 4 process node has Intel’s highest Day-Zero yields in a decade.www.tomshardware.com
I agree. Especially for chips with very complex logic. Design cycles will be quicker and cheaper, which should accelerate innovation. On the other hand, let's not kid ourselves, chiplet designs may have power and performance challenges compared to single die designs for some applications. But I think, overall, chiplets are a huge win for the industry.Chiplets really are going to disrupt the foundry business. Just wait and see......
Yeah I don't think you can find anyone who would say the process tech was in a great place for BDW or ICL, nevermind CNL (even if I think it would be funny to see it plotted here). Either way skylake and tigerlake were very clearly fine on the yield front given how intel made a boatload of those medium die sized client parts and large DC parts without having margins fall off a cliff.That's a pretty low bar though. Intel had yield problems on launch day with both 14nm and 10nm.
For Meteor Lake, are they referring to yield of assembling the tiles?Yeah I don't think you can find anyone who would say the process tech was in a great place for BDW or ICL, nevermind CNL (even if I think it would be funny to see it plotted here). Either way skylake and tigerlake were very clearly fine on the yield front given how intel made a boatload of those medium die sized client parts and large DC parts without having margins fall off a cliff.
Also I just noticed the plot says they are equalized for a 100mm^2 die. No clue why they chose to have it be a hard to see grey (especially when it is good news like that), but here we are.
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Should the yield of "Intel 4" in Meteor Lake be calculated only based on the CPU tile? Since all the other parts are made by tsmc N5/N6.For Meteor Lake, are they referring to yield of assembling the tiles?
Could be yield of the full system in package, but they also had some talk about great yields of the full packaging process too.Without supplying desktop CPU, Meteor Lake CPU launch date still 2 months later than usual.
Not a good sign for good yield.
I suspect it has to do with packaging complexity with the various chiplets than actual yield issue is the reason for the delay.Without supplying desktop CPU, Meteor Lake CPU launch date still 2 months later than usual.
Not a good sign for good yield.