My assumption is a roughly a quarter for fab processing time and 4-6 weeks for packaging so 17-19 weeks overall. Add in time to get some volume built up and I figure you need to start running the volume you want to sell at the end of the year by June.
Your assumption is too optimistic. And the reason for that is shipping time and advanced packaging. With the one quarter cycle times of N2 and slightly less than a quarter cycle times on N3 Apple needed wafers to start in December just to have volume of final assembled iPhone pro only by September (10 months). And everyone knows Apple runs the most efficient supply chain network on planet Earth. An 18A wafer from Oregon and Arizona is much further from the factories in China Vietnam and in Apple's case now India than a TSMC fab that is just across the pond. Most of the non flagship laptops launch (especially the higher volume more mainstream models) in January for a given new CPU generation. So if laptop OEMs were as fast as Apple, 18A cycle time ~ N3B cycle time, and we waved a magic wand and moved D1 and Fab 42-62 to Taiwan Intel would have needed to start production wafers no later than March/April. Realistically 18A HVM would have needed to have started sooner because Intel CPUs would have DRAMATICALLY longer assembly test times due to the use of advanced packaging and longer transit times for the finished CPUs to get shipped from NM to East Asia. And if we are talking about the early enablement laptops that will launch this year rather than the tidal wave in January those wafers would have needed to have started early this year or even late last year.
Many of these decisions were made a while ago.
Exactly if this rumor is true N2 for a compute die in 2026 would have needed to have been irreversibly locked in 2022, and given Intel's propensity to do all of their IPs in house they would have needed to have started N2 enablement work back in like 2020-2021. But given how slow intel products are and how often things are delayed, let's call that enabling work happening in 2019-2020. Interesting, a certain pair of managers whose names may or may not rhyme with Kim Stellar and Saga Koduri were in charge of Intel's architecture team at the time and were rumored to be heavily in favor of porting designs intended for Intel Si to TSMC...
And Clearwater Forest is not really a high-volume high-value product, BTW. According to Intel, these E-core Xeons have limited interest from the industry partners. We could corroborate that statement with Ampere Computing's poor performance.
TBF that wouldn't have really been expected at the time, otherwise Intel wouldn't have been disappointed in SRF's softness.
I can totally relate, it wouldn't be prudent to use 18A on a high-volume or high-value product.
Like all of Intel's mainstream CPUs in 2026-2027, all of their premium CPUs in 2026, and those higher volume dies for Novalake. IF would gladly give up all of desktop for all of mobile (80% of the volume). But if rumors are correct and it is just the desktop i9/i7. We are talking also a minority of the remaining 20%, and there are rumors that point to 100% of the SOC and graphics dies being 18A too. But you know what, maybe you're right... Maybe one die for ~5% of the client NVL chips is higher volume than 95% of the compute dies + 100% of supporting dies.
Especially since N2's lifecycle is ~6 months ahead of 18A's lifecycle.
N2 is clearly the prudent move for Intel's high-volume or high-value products.
For foundry sure. 1.0 PDK was first. Risk production was also first. But I can't think of Intel, Micron, Ti, OnSemi, Infenion, SK, Kioxia, Toshibia, Fujitsu, or IBM ever declaring risk production before starting product HVM. The products just come out. And unlike the say TSMC where the product is wafers and ramp starts when production wafers start, someone selling chips (like say Micron) would say "we are ramping our new product" only once shipments for revenue started, not during the samples phase (which I guess is the closest thing to foundry risk production). Combine that with the DD = 0.1 call late last year, and production wafers clearly having started already. The public announcements paint a clear picture that foundry readiness lags behind where process health is (as opposed to TSMC where the two are in lock step). Now if you want to believe all 18A products will slip to March 2027 and DD was made up, that is your own prerogative
I think there is a lot of parallel design efforts still going on. And Sometime Intel renames one lake to another lake for marketing purposes.
Can you list one example in the past 50 years of this happening.
Remember when Arrow lake was 20A. Then it was TSMC N3 on some skus. Then it was N3 on all skus. There are 1 or 2 refreshes coming as well.
Since the 20A sku was canned right before ARL launched the N3 one would have needed to have been designed first, with 20A being an additional thing. Unless you believe that Intel was going to design and validate an N3 version with no intention to EVER productize it, ARL was NEVER all 20A.
Don't get too married to what Intel says or even what they are sampling. The roadmap will change significantly by mid 2026
So by mid 2026 Intel will change their roadmap for products launching before 2026 and in 2026? No they won't. Everything happening for in 2026 was predetermined years ago. Whatever the results are have 0 to do with any calls made this year, last year, or next year.
Well, if Patti O'Furniture said, it must be true.
Yes, that sort of thing will. He would know what chips were using, and you can't port an 18A design to N2 in 1 year. If you believe anything else, you would be so dense you would make W look like a low-K dielectric. But I will leave it there, since I feel like I am talking to a wall with folks like you. You don't use factual evidence or logic in your arguments, and ignore any and all who use logic and reason or attempt to explain things to you in the hopes of you learning and improving. I enjoy teaching and sharing what experience and knowledge I have accumulated, but I don't enjoy spinning my tires in the sand...