Intel Provides Update on Internal Foundry Model
- Thread starter Daniel Nenni
- Start date
So either intel forged data on four academic papers across two industry conferences; or a random guy on the internet is incorrect on his analysis. I know which I would bet on being more likely.
Transistor performance for "3nm" class nodes in 2023 and early 2024.
IDEM and the VLSI symposium have given us a good amount of data to pour over for the node landscape from TSMC and intel in 2023/early 2024. Samsung having declined to give any details on the "in production" 3GAE that has "perfect yields" (their words not mine). I thought it might be nice if that...
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Intel is not using N3 for CPU chiplets. They are using N3 for GPUs and other supporting chiplets so I think it is a cost and capacity issue. Intel Foundry wafers will never be more cost effective than TSMC. Performance is Intel's niche, and it's a good one to have, my opinion.
Yeah, there's not even a comparison with TSMC N4, interesting.
hist78
Well-known member
There is another strange thing in the IDF presentation. In the IDM 1.0 slide, Intel only listed its gross margin up to 2014. Intel had maintained >50% gross profit margin up until Q1 2022 and only announced IDM 2.0 strategy in March 2021. Why Intel wants to skip 2015 ~ 2022 gross profit margin data?
The chart would look too busy if it said
1 node done
2nd node almost done
Rest on track; leadership on 18A
Since 4 is not quite done, they just lumped 7 and 4 together with ‘2 nodes essentially done’
tooLongInEDA
Moderator
I'm more interested in the financial numbers here. Putting my sceptical hat on. Since the analysts on the call don't seem to have bothered to.
The example on Slide 12 shows a current Intel foundry operating margin (OM) of -18% (which may or may not be accurate - but it's Intel's own number).
The transcript claims that they aim to reach 60% GM and 40% OM in foundry. Slide 15 (don't these analysts question anything ? this has neither X or Y axes !!!) seems consistent with that - implying -18% today and +40% at some unspecified time in the future.
Now on Slide 6. Dave Zinsner is telling us that he's currently saving $3bn a year in foundry costs and will be saving $8-10bn a year by end 2025. So that's the sort of ballpark figure you'd need to turn round the OM from -18% to +40% - but perhaps not quite enough.
So how do you save $10bn a year over 2-3 years on a business with a $20bn a year run rate ? Is Slide 15 (where we should assume the Y axis covers 3 years from the other data presented) possible ? Remember, Intel has more processes to run than ever now. Has anyone done that scale of OM change that quickly before ?
Slide 19 doesn't seem to stack up to $8-10bn a year - that totals only $4-5bn "identified" today. Where's the other $4-5bn coming from ?
Apart from that, 40% OM does seem extraordinarily high for any business. Yes, TSMC's getting this as the unique leader in a strong market where they have a lot of pricing power. But don't those dynamics change with all the new investment and competition currently planned ?
The example on Slide 12 shows a current Intel foundry operating margin (OM) of -18% (which may or may not be accurate - but it's Intel's own number).
The transcript claims that they aim to reach 60% GM and 40% OM in foundry. Slide 15 (don't these analysts question anything ? this has neither X or Y axes !!!) seems consistent with that - implying -18% today and +40% at some unspecified time in the future.
Now on Slide 6. Dave Zinsner is telling us that he's currently saving $3bn a year in foundry costs and will be saving $8-10bn a year by end 2025. So that's the sort of ballpark figure you'd need to turn round the OM from -18% to +40% - but perhaps not quite enough.
So how do you save $10bn a year over 2-3 years on a business with a $20bn a year run rate ? Is Slide 15 (where we should assume the Y axis covers 3 years from the other data presented) possible ? Remember, Intel has more processes to run than ever now. Has anyone done that scale of OM change that quickly before ?
Slide 19 doesn't seem to stack up to $8-10bn a year - that totals only $4-5bn "identified" today. Where's the other $4-5bn coming from ?
Apart from that, 40% OM does seem extraordinarily high for any business. Yes, TSMC's getting this as the unique leader in a strong market where they have a lot of pricing power. But don't those dynamics change with all the new investment and competition currently planned ?
delong.height
Active member
So that $10B saving is a combination of internal BUs and IFS, it's not $10B on IFS only.
And yes, they do have more process to run but they will only have 3~4 processes that're running by 2025 because 18A is compatible with 20A, and Intel 3 is compatible with Intel 4. So eventually, they will only have Intel 16, Intel 7, Intel 3, Intel 18A.
hist78
Well-known member
The availability of IFS PDK is a big concern for analysts. TSMC is going to start N2 risk production in 2024 and HVM in 2025. In the coming several months it's probably the time for those major fabless companies to decide where they will manufacturer 2nm generation of chips.
Intel confirms it will be a long slog for its foundry business
Intel tells Wall Street analysts that the first customer for its foundry business will likely be announced in the second half of this year.
www.marketwatch.com
tooLongInEDA
Moderator
Didn't Intel already have 18A testchips delivered to customer(s) ? Sure I remember reading that. Are those done with a pre-production PDK ?The availability of IFS PDK is a big concern for analysts. TSMC is going to start N2 risk production in 2024 and HVM in 2025. In the coming several months it's probably the time for those major fabless companies to decide where they will manufacturer 2nm generation of chips.
Intel confirms it will be a long slog for its foundry business
Intel tells Wall Street analysts that the first customer for its foundry business will likely be announced in the second half of this year.
hist78
Well-known member
Nvidia Jensen Huang mentioned this Intel test chip while he was in Taiwan for the Computex Taipei 2023. He didn't elaborate the details of the test chip or who designed it.
This brings us to the next question: isn't Intel 4 supposed to be "fully" done in order to be ramping Meteor Lake production now?
I always took “intel 4 being for all intents and purposes done” as the process is done even though meteorlake hasn’t launched yet. I could also see it being a statement that the ramp is still ongoing. Either way the silicon will speak for itself if intel 4 was fully cooked or not.
Intel 4 and Intel 3 have full PDKs and Intel 4 chiplets are in production. I do not know of any Intel 3 foundry design starts, this is according to the ecosystem at the TSMC Symposium. I will ask again at the Samsung Symposium next week and DAC next month. The ecosystem knows...
But again a TSMC process is not done until Apple gets wafers and this is a complex SoC manufactured in the millions so it is a different type of done.
hist78
Well-known member
This slide is a comparison based on HVM dates but it must be based on the similar technical matrix (such as PPA) or loosely based on the same "generation". Otherwise it can be an apple vs orange situation and much less meaningful.
Does it mean Intel believes PPA for Intel 20A is similar to TSMC N3 or N3*? Or Intel 18A is similar to TSMC N2?
The slide says timing so I believe it is a production ready date. I have no idea how they matched processes with TSMC. In my view, moving forward, Intel will be known as the high performance leader while TSMC will have density and low power. As for who is first that will depend on how you measure. A good measurement would be when the PDK is production worthy. That will be bad for Samsung
but a fair measurement for Intel and TSMC. This would be the foundry PDK so Intel 3 and 18A. A chiplet PDK (Intel 4 and 20A) is much easier and is not an apples to apples comparison. It is the difference between an IDM foundry and a pure-play foundry.An SoC PDK (Apple) is a pretty good balance of performance, density (area) and power. CPUs, GPUs, and AI chips are high performance. IoT, automotive, and other battery powered applications are low power centric.
Analyst note and he is not wrong, but remember, the foundry business is a marathon not a sprint:
Bernstein analyst Stacy Rasgon, who has a market perform rating and per-share price target of $30 on Intel, said that even though the economics of the foundry look "unsurprisingly horrible" right now, Intel fully recognizes it needs to develop a "structurally more efficient cost structure."
"Up until this point, however, we have been unclear where those [cost of goods sold] savings are coming from (or indeed, whether the company even knew)," Rasgon wrote in an investor note, referencing Intel's comments that it will pull $8B to $10B in costs out of the business, including roughly $3B this year.
"However, they did identify at a high level a number of efficiencies (expedites, sampling, test times, architecture etc) with more (utilizations, steppings, etc) on top that they believe can account for $4-5B and in general do not appear to be hugely revenue-dependent (important)."
Rasgon added this would probably allow Intel to improve gross margins by roughly 10 points - though not get the company to its 60% target - but seeing as there is a significant amount of costs to take out, identifying and admitting to the discrepancy between the company and its competitors is "probably a healthy exercise."
Bernstein analyst Stacy Rasgon, who has a market perform rating and per-share price target of $30 on Intel, said that even though the economics of the foundry look "unsurprisingly horrible" right now, Intel fully recognizes it needs to develop a "structurally more efficient cost structure."
"Up until this point, however, we have been unclear where those [cost of goods sold] savings are coming from (or indeed, whether the company even knew)," Rasgon wrote in an investor note, referencing Intel's comments that it will pull $8B to $10B in costs out of the business, including roughly $3B this year.
"However, they did identify at a high level a number of efficiencies (expedites, sampling, test times, architecture etc) with more (utilizations, steppings, etc) on top that they believe can account for $4-5B and in general do not appear to be hugely revenue-dependent (important)."
Rasgon added this would probably allow Intel to improve gross margins by roughly 10 points - though not get the company to its 60% target - but seeing as there is a significant amount of costs to take out, identifying and admitting to the discrepancy between the company and its competitors is "probably a healthy exercise."