Lip-Bu mentioned that he needs to repair Intel's balance sheet. We all know who caused significant damages (debt level) to Intel's balance sheet.
Intel CEO Lip-Bu Tan’s Letter – 2024 Annual Report to Security Holders
- Thread starter XYang2023
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I am sorry, numbers don't support this statement (see below). I think you are being uncharitable to Pat Gelsinger. The amount of investments he had to make to get Intel out of being stuck in 10nm debacle to now Intel 18A that compete with TSM & build the shells required for Intel Foundry but still only increase the Intel's debt by $10B to $13B is remarkable imho. That is puny compared to $25B capex each year they were doing during his time there.
Sure he hired a bunch of people during his initial tenure but they had to meet the increased Post Covid demand for their client and server products. Then ChatGPT spoiled the party by hijacking the server CPU spend, all the while client computing went through a slump post 2022. He said it himself that he could not go to his TD team and ask them to catch up on node process all the while cutting cost in one of the investment conferences (right after Q3'2024 earnings, iirc).
In my book, he did a good job as CEO, he was dealt a bad hand and he played as best as he can with that. I know others here disagree. He is not without shortcomings though,1) he did not manage expectations for Intel Foundry, 2) He did not cut costs as soon as the 2023 started (Dividend should have been cut instead on reduced in Jan 2023, may be even layoff should have started around that time), 3) did not capitalize on the AI (he should have targeted AI training with GPGPU rather than AI inference from the beginning with AI PC). But hindsight is 20/20.
His strategy was conditioned on US supports. But till now, Intel has only received 2B from CHIPS Acts. We don't know what Trump will do regarding CHIPS Acts in the future.
At the same time, Intel has spent 30-50B to align with Chips Acts.
One news report mentioned Intel has spent 7B on just Ohio. Those assets are sitting there and produce nothing.
If PG would not be such aggressive, Intel should have enough capital to fund other areas such as data centre AI without shedding assets (ownerships in Ireland fabs, ownership in Arizona fabs, Altera, Mobileye etc).
MKWVentures
Moderator
that was very telling (I like the honesty). they have some issues over the next few years that limit everything else they are trying to do.
Regarding the balance sheet, I believe they can take the following actions:
1. Divest Altera and Mobileye.
2. Reduce capital expenditure by reusing existing fab space.
3. Secure 1–2 large fab customers.
4. Explore potential partnerships, alliances, or joint ventures with IFS.
Additionally, they should accelerate their data center AI efforts and develop custom AI and x86 solutions.
CHIPS act is passed on the Congress by bipartisan support. It likely it will survive. Trump's contention with act was Biden admin was giving money to companies like TSMC to come to USA as opposed to tariffs and also some Republicans seems to be against DEI stipulations in the act. What is wrong with formulating a strategy that involves govt support? TSMC itself was founded with Taiwanese govt support and to this day they get preferential treatments in Taiwan. Imo Intel should have gotten more support from USG and sooner.
When you are a new comer in an industry, you should be the one putting your foot forward not your customer. TSMC can plan their expansion based on customer demand because they are established and they know their customers road maps well in advance. Intel Foundry as a emerging player don't have that luxury. When test chips run by customer yields good results and they come to place an order and you tell them let me build this fab for 3 years and service your orders, they will laugh at you to your face. Plus the land and fab buildings are amortized over 10 to 15 years time frame in your P&L. It is always prudent to have these built in advance especially you are planning out your business. If day after tomorrow, Trump announces a very restrictive tariffs on semi imports tomorrow, these "waste" as you call them will be invaluable assets. Even today as you know the construction is ongoing at Ohio one, it just going to be equipped later for HVM.
They still have $20+B in cash and short term investments, is that insufficient to fund these data center AI products? To be honest, GPUs were not Intel's strong suit, they are primarily a CPU company with some GPU offerings. I don't think lack of investment during Pat Gelsinger tenure in AI GPU is the reason they missed the AI wave. They missed this a long time ago by not having a mature GPGPU platform and software stack to go with it.
Okay, we will have to agree to disagree on that one.
1- That was already the plan under Pat.
2. Older fabs can't be fitted with EUV machines per my reading of things (please someone let me know if I am being ignorant here).
3. Was Pat Gelsinger against getting 1-2 larger customers?
4. I hope you understand that Ireland and Arizona SCIPs which you call "shedding of assets" are exactly this idea but on fab level rather than business unit level.
Anyway, next two years of Intel is still Pat Gelsinger's Intel in terms of products and process. Whether Bad or Good, we will see really what happens.
MKWVentures
Moderator
New Fab customers are 2 years out best case for meaningful revenue. How can a customer commit to Intel with all this uncertainty?
When you look at re-use vs greenfield, you often find reuse isnt as cheap as hoped (There are lots of details why). reusing old fabs is not option (maybe 42?)
Best capex reduction is using Oregon more, filling up Ireland and Filling up Arizona (Neither shows as full). There is no need for any more fabs after that until at least 2030.
Oregon full+Fab 52 full is best hope IMO (other than the 2020 solution). Keep other products outsourced to prevent cashflow issues. Add Fab 62 if the demand shows in 2027-28.
You can do a pretty simple spreadsheet that shows the financial issues for IFS and how there are no easy answers. I think Tan will have a more drastic update by summer.
I lived in Singapore for a few years, and never heard of him, nor about EDA software back in 200X. The semi design, and R&D side was much more low profile.
Real men had fabs, and most of semi community talk was about them, and actual manufacturing.
That is true. Friends and family had no idea what I did for a living (EDA/IP) until I started writing about it on SemiWiki. The unsung heroes of the semiconductor industry. TSMC is the one that made us EDA/IP people famous. It is all about the ecosystem, absolutely.
I do not think Intel will see meaningful IFS revenue until 2030 (14A). I remember Pat Gelsinger saying that Intel had secured commitments for its foundry business amounting to something like $10-15 billion in "lifetime" revenue. We all laughed out loud at "lifetime revenue", had not heard that one before.
MKWVentures
Moderator
I do not think Intel will see meaningful IFS revenue until 2030 (14A). I remember Pat Gelsinger saying that Intel had secured commitments for its foundry business amounting to something like $10-15 billion in "lifetime" revenue. We all laughed out loud at "lifetime revenue", had not heard that one before.
LIfetime revenue is what you always say when you are a start up getting design wins with no revenue. I have said it many times. Just not with an established company
Intel also said they expect 15B in ANNUAL Revenue by 2030. Intel planned 6+ new fabs and now plans 1. Its hard to recover from that. Tan is underpromise, over deliver.... a big change for intel.
Side note: TSMC people are legit talking about 25K+ wafers per month of N2 by end of the year. That is about 5x more than we expect from Intel.
Is TSMC N2 High volume in 2025 a real thing?
Fab 42 is already partially tooled for Intel 18A and rest being tooled for UMC+Intel 12nm per what I heard online.
Fab 52 will also be 18A and Fab 62 is likely will be "shelled" for future.
I keep hearing that Intel can't fill its fabs but I don't get it
,Intel sells about 35 million units of notebook CPUs each quarter. That is 140Mu per year (on the lower end of estimate). For panther lake, the compute tile is about 114sq-mm. If I use online yield calculators with D0=0.2, that gives 410 good dies per 300mm wafer. That needs about 341,463 wafers per year which translates to 28,455 wafer per month. If we assume, Intel fab 42 and 52 are about 25,000 wafer start per month capacity. They can easily fill 1 fab for notebooks alone and partially load another fab with this. right?
If I assume a worse D0 (as rumored by "internet"), they need to run more wafers to get the same output, so that means they can fill the fab even more. Even if we assume that Intel bins the defective dies to lower tier SKUs, they still should get about 25,000 wafer per month (assuming 500 dies per wafer) once things go into full HVM.
Now add Clearwater Forrest Xeon, Diamond rapids Xeon, future desktop product - Nova lake and external customer can surely fill 2 fabs, right?. Sever CPUs account for about 4Mu each qtr. and desktop is another 8-10Mu each qtr.
And these products are more core and die size is likely bigger than 114 sq-mm I considered for panther lake or more dies per chip with advanced packaging. This means they need more wafer starts.
I do understand that server CPUs ramp much slower. But still, I feel like they should be able to load Fab 52 fully and 42 partially with 18A when things move in 2026+.
Am I missing something here? Are Intel fabs bigger and have more capacity than of 25,000 wafer start per month? I also saw that TSM's Arizona first fab is 20,000 wspm only. If we assume Intel's fab are similar size, I don't see a problem here in terms of filling the fabs. Please let me know if I am making some wrong assumptions. Thanks.
I have been in the foundry business for 30+ years and have never heard the term lifetime revenue before. An IDM might be able to calculate that but not a foundry.
TSMC N2 will hit HVM at the end of the year I am told. The question I have is who will ship the first N2 chips? Apple in Q4 2026? Or something sooner because TSMC is going to be making a whole lot of N2 wafers in 2026.
I believe you are referring to Lifetime Deal Value that Intel said they have of about $15B for Intel Foundry in mid 2024 (before signing up AWS as customer in Q3'24).
On a recent investor conference Dave Zinsner (CFO) said "we are not going to provide frequent update of Lifetime value for foundry anymore as that don't really mean anything until we get revenue" (paraphrased). Of course, after PG was "retired".
You are correct. I was there and it was funny at the time because it was a new phrase. We call them wafer agreements:
In February 2024, during Intel's inaugural Foundry event, CEO Pat Gelsinger announced that Intel Foundry had secured design wins across various process generations, including Intel 18A, Intel 16, and Intel 3. These commitments, encompassing both wafer production and advanced packaging, were projected to have a lifetime deal value exceeding $15 billion.
MKWVentures
Moderator
Fab 42 is already partially tooled for Intel 18A and rest being tooled for UMC+Intel 12nm per what I heard online.
Fab 52 will also be 18A and Fab 62 is likely will be "shelled" for future.
I keep hearing that Intel can't fill its fabs but I don't get it
Intel sells about 35 million units of notebook CPUs each quarter. That is 140Mu per year (on the lower end of estimate). For panther lake, the compute tile is about 114sq-mm. If I use online yield calculators with D0=0.2, that gives 410 good dies per 300mm wafer. That needs about 341,463 wafers per year which translates to 28,455 wafer per month. If we assume, Intel fab 42 and 52 are about 25,000 wafer start per month capacity. They can easily fill 1 fab for notebooks alone and partially load another fab with this. right?
If I assume a worse D0 (as rumored by "internet"), they need to run more wafers to get the same output, so that means they can fill the fab even more. Even if we assume that Intel bins the defective dies to lower tier SKUs, they still should get about 25,000 wafer per month (assuming 500 dies per wafer) once things go into full HVM.
Now add Clearwater Forrest Xeon, Diamond rapids Xeon, future desktop product - Nova lake and external customer can surely fill 2 fabs, right?. Sever CPUs account for about 4Mu each qtr. and desktop is another 8-10Mu each qtr.
And these products are more core and die size is likely bigger than 114 sq-mm I considered for panther lake or more dies per chip with advanced packaging. This means they need more wafer starts.
I do understand that server CPUs ramp much slower. But still, I feel like they should be able to load Fab 52 fully and 42 partially with 18A when things move in 2026+.
Am I missing something here? Are Intel fabs bigger and have more capacity than of 25,000 wafer start per month? I also saw that TSM's Arizona first fab is 20,000 wspm only. If we assume Intel's fab are similar size, I don't see a problem here in terms of filling the fabs. Please let me know if I am making some wrong assumptions. Thanks.
What percentage of Intel wafers today are 7nm or older? Does Raptor Lake outsell meteor Lake? How does Granite Rapids volume compare to sapphire/emerald?
It is hard to ramp a new fab and be cost effective. When the process is very expensive, it is even harder
what do you think the wafer cost will be for 18A in Fab 52?
You have in a sense. When TSMC says hey when all is said and done this Fab will cost us x NTD. That is effectively a sum of lifetime deal values across construction and tool vendors. When ASML talks about their current order book for x type of scanner being however many billion dollars, that is literally lifetime deal value.
TSMC could easily calculate that. Every TSMC customer has a wafer deliver schedule. Sum all of the wafers across the lifetime of a contract. Multiply by the ASP, and bata bing bata boom lifetime deal value. Sum LDV across every existing contract and you have total LDV. It doesn't really make sense to report that since TSMC has tens of billions in revenue per year right now (what investors care about) and TSMC'S total LDV is likely in the trillions of dollars over their decade order book. Since much of TSMC's buisness is long term contracts their total LDV growth would presumably be much lower than the revenue growth in a given year, so it would look less impressive to focus on that than revenue/margin growth.
Doesn't seem like more than Intel since they would be doing 2 generations of client on 18A with supposedly even more internal content than Pantherlake. Meanwhile TSMC would be early in their non Apple ramp. Also just matching up the fabs, 2 N2 fabs is in fact fewer fabs than D1 pilot line plus 2-3 Intel Arizona fabs. 2027 TSMC will almost assuredly have more 2nm capacity than Intel though once you have all the mobile guys, AMD, and multiple generations of iPhone saturating the market. Counting the fabs, presumably smaller (or even no) D1 pilot line and 3 AZ fabs versus 4-5 N2 fabs.
I've been saying this for a long time. Back in their prime Intel couldn't even meet demand with over 100K WSPM (similar to the combined N5 + N3 capacity of Fab18 phases 1-6). To say Intel can't fill one fab would require Internal demand to be less 20% of what it used to be. Intel has fallen, but not that far.Fab 42 is already partially tooled for Intel 18A and rest being tooled for UMC+Intel 12nm per what I heard online.
Fab 52 will also be 18A and Fab 62 is likely will be "shelled" for future.
I keep hearing that Intel can't fill its fabs but I don't get it
Intel sells about 35 million units of notebook CPUs each quarter. That is 140Mu per year (on the lower end of estimate). For panther lake, the compute tile is about 114sq-mm. If I use online yield calculators with D0=0.2, that gives 410 good dies per 300mm wafer. That needs about 341,463 wafers per year which translates to 28,455 wafer per month. If we assume, Intel fab 42 and 52 are about 25,000 wafer start per month capacity. They can easily fill 1 fab for notebooks alone and partially load another fab with this. right?
If I assume a worse D0 (as rumored by "internet"), they need to run more wafers to get the same output, so that means they can fill the fab even more. Even if we assume that Intel bins the defective dies to lower tier SKUs, they still should get about 25,000 wafer per month (assuming 500 dies per wafer) once things go into full HVM.
Now add Clearwater Forrest Xeon, Diamond rapids Xeon, future desktop product - Nova lake and external customer can surely fill 2 fabs, right?. Sever CPUs account for about 4Mu each qtr. and desktop is another 8-10Mu each qtr.
And these products are more core and die size is likely bigger than 114 sq-mm I considered for panther lake or more dies per chip with advanced packaging. This means they need more wafer starts.
I do understand that server CPUs ramp much slower. But still, I feel like they should be able to load Fab 52 fully and 42 partially with 18A when things move in 2026+.
Am I missing something here? Are Intel fabs bigger and have more capacity than of 25,000 wafer start per month? I also saw that TSM's Arizona first fab is 20,000 wspm only. If we assume Intel's fab are similar size, I don't see a problem here in terms of filling the fabs. Please let me know if I am making some wrong assumptions. Thanks.
MKW is right here. Because of how long it takes to go from ink to revenue, there would be no other way to show growing momentum than LDV. Intel could have theoreu won every fabless design post 2026 and IFS would have exactly as much revenue in 2025 as now. LDV also shows something of a 100% certainty lower bound for what returns will be made based on the current order book. As a bonus I feel like I have also seen LDV quoted pretty frequently for big projects/deals/partnerships that span over long time horizons as in addition to MKW's mention of a start up wanting to show their growth/momentum.
No. The current plan is to build the same number of fabs but slower. Now if Germany gets done this decade... Ehhh, we'll see since Ohio got pushed out towards the end of the decade. But as for 18A specifically they wanted to do 5 (not 6) and now they are doing 3 (not 1).
1) It is way to early to say that
2) We won't really see the impact of Tan until 2030 since everything before that was set in motion or mostly done under Pat. Just like how won't see the full impact of Pat until 2026, and how we have only started to see the impact of BS's decisions recently.
3) His claims and goals don't really seem all that different than Pat's. His demeanor may be different, but the content of what was said not as much