ICC2 is improving RunTime. Hopefully, other improvements follow.

[OneBraveSoul]

All,

Who I am:
Perennial Block Owner, from RTL start to finished gates. Design Implementation and Physical Design.
My first tapeout was in 1997; my last tapeout was in 2014 in Global Foundaries.
2015 has been spent in PPA initiatives. I am always following the direction of a chip lead.

What project have I been working?
Graphic Core PPA Improvement Initiatives

What tool will I review?
ICC2. Newest release from Synopsys for Digital Place and Route.

How much have I used it?
2 months.

The problem ICC2 has addressed well?
Runtime improvement. 1 example placement: 105 hours to 10 hours. Similar QOR results.

Problems ICC2 has created?
1) The runtime improvement was achieved at the reduction of attributes saved in the database. This inhibits predicting power comparisons between runs. Grabbing the wire cap, wirelength ,pin cap of global routing during place appears to maybe be possible , but it used to be an exact attribute. This may just be an ease-of-use issue, but so far, results appear to indicate that these values aren't fully available. We can measure power at route, but then, it is often too late to change management direction.

2) Place now appears non-deterministic in result. The same input data, the same input scripts, the same version of the tool, will now vary in QOR result. Hopefully , this is a bug to work out. For 2 months--June 2015 and July 2015, this has been the case. I am not indicating bad results here; I am just indicating different ones. This non-determinism used to be restricted to routing on several cores.

3) Commands and variables have changed from previous ICC. I am not sure this improves anything. The same thing is present with gui commands and generating design maps. Change in commands doesn't help.

Problems ICC2 appears to solve:
1) Merging of frames and LIBs into 1 NDM (data model) streamlines the use of input library data.
2) High fanout synthesis has now moved to the end of the placement flow. Initial DRC fixing now happens first.

Both of these changes mean that wirelength can now be used to compare the tradeoffs of varying floorplans.
In ICC, since DRC was last, and high fanout synthesis first, there was often a disconnect. The floorplan judged to be the best during design planning and at the beginning of an atomic placement , would often not be the best come the end of placement. For two months, in iterative placements, ICC2 has shown a correlation between the location of placement magnets---ports, memories, channels, and block shape--during low effort placements
and the most optimized floorplan.

How does this compare to other improvements I am following?
I do floorplan builds in Cadence FirstEncounter between my ICC2 experiments. I will continue to do those there. FE continues to make improvements without changing the data I am able to report and interact with.

What have I heard?
A good flow in Aug 2015, is using ICC2 for placement, and switching back to ICC for CTS and route until the bugs are ironed out. Heresy, of course, from deepchip.com.

I look forward to feedback from other users. Thank you.


Reference: Post an EDA Tool Review on SemiWiki and get $250!

 

[Paul McLellan]

I don't have any personal experiecne with ICC2. But it is not totally new. if you had read me interview with Antun Domic you would know:
The focus recently has been introducing ICC2 (Synopsys’ place & route system, called Newton internally). One of the rare occasions that an EDA company looks at the problem completely from scratch: new database, new optimization, new clock-tree synthesis. The only parts kept were placement and routing (which is under 25% of the code).

So placement is one of the new things but one that OneBraveSoul uses the old version of. Curious. Heuristic algorithms are just not predictable

 

[Tom Dillinger]

OneBraveSoul:

Thanks for the feedback on ICC-2! Your article did prompt some additional questions...

(1) re-partitioning into larger block sizes

I understand that one of Synopsys' goals for the NDM is to enable much larger block sizes to be used in the ICC-2 physical design flow. Have you been able to indeed verify that the model capacity has increased, leveraging the improved multicore runtime? Do you foresee your team re-partitioning designs differently, as a result?

(2) technology design rule complexity

Another Synopsys goal was to better manage the technology rule complexity, specifically cell placement and routing restrictions associated with multipatterning and FinFET technologies. Were your experiments using a technology with (multiple) DPT metal layers? Did you use a lot of non-default routes (with area pins on cells) for those layers?

Did you see an improvement in post-route DRC results with ICC-2 compared to ICC?

(3) global placement improvements

Without divulging too many details, how hard were your designs "pushing the technology"? Synopsys has supposedly focused on the global placement algorithms, for allocation of routes on upper metal layers for performance optimization? Did you see performance-driven improvements with ICC-2 (say, in terms of TNS or WNS, compared to ICC)?

Thanks in advance for the insights!

-chipguy

 

[OneBraveSoul]

Placement and Route have changed....

I don't have any personal experiecne with ICC2. But it is not totally new. if you had read me interview with Antun Domic you would know:
The focus recently has been introducing ICC2 (Synopsys’ place & route system, called Newton internally). One of the rare occasions that an EDA company looks at the problem completely from scratch: new database, new optimization, new clock-tree synthesis. The only parts kept were placement and routing (which is under 25% of the code).

So placement is one of the new things but one that OneBraveSoul uses the old version of. Curious. Heuristic algorithms are just not predictable

OneBraveSoul--> In ICC, I can run the same inputs , with same scripts, 8 different times, and the resulting placement will be the same.
In ICC2, this is the not the case.
In ICC, only route is non-deterministic because it is done on multiple cores.

In the quote you mention above, Antun states the algorithms for placement and routing were kept the same; however,
execution of the ICC2 tool indicates they are no longer the same. Now, DRC cleanup is done first; high fanout synthesis
and delay optimization has moved to the end. Placment is now different. Routing also is different; without giving too many
details, coorelation of global route to route is having a problem.

Enjoying the runtime improvement.

--BNS

 

[OneBraveSoul]

OneBraveSoul:

Thanks for the feedback on ICC-2! Your article did prompt some additional questions...

(1) re-partitioning into larger block sizes

I understand that one of Synopsys' goals for the NDM is to enable much larger block sizes to be used in the ICC-2 physical design flow. Have you been able to indeed verify that the model capacity has increased, leveraging the improved multicore runtime? Do you foresee your team re-partitioning designs differently, as a result?

(2) technology design rule complexity

Another Synopsys goal was to better manage the technology rule complexity, specifically cell placement and routing restrictions associated with multipatterning and FinFET technologies. Were your experiments using a technology with (multiple) DPT metal layers? Did you use a lot of non-default routes (with area pins on cells) for those layers?

Did you see an improvement in post-route DRC results with ICC-2 compared to ICC?

(3) global placement improvements

Without divulging too many details, how hard were your designs "pushing the technology"? Synopsys has supposedly focused on the global placement algorithms, for allocation of routes on upper metal layers for performance optimization? Did you see performance-driven improvements with ICC-2 (say, in terms of TNS or WNS, compared to ICC)?

Thanks in advance for the insights!

-chipguy

----Given the runtime improvement, re-partitioning definitely is a possibility. 2.5 Million Gates, 10 hours to CreatePlacement. Good visibility into bad starts.

----10nm. DP is definitely involved.

----No data to present on ICC versus ICC2. Placemens haven't gotten worse results. The only factor I have noticed is I can get slightly different results, varying in level of timing, congestion, power improvments at the end of placement in ICC2 with multiple runs of the same input data.

---- Post Route and global route don't currently correlate to routability, mainly due to DoublePatterning. Good idea to switch back to ICC for routing if you need to tapeout in August 2015.