Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/threads/huawei-the-leader-in-chinese-semiconductor-development%E2%80%A6-%E2%80%98life-or-death%E2%80%99-for-smic-5nm-mass-production-next-year.22690/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021770
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

Huawei, the leader in Chinese semiconductor development… ‘Life or death’ for SMIC 5nm mass production next year

Daniel Nenni

Admin
Staff member
China's largest foundry SMIC to start full-scale 5nm operation next year; lack of essential equipment such as EUV… 5nm yield expected to be around 30% “SMIC's 5nm process price likely to be 50% more expensive than TSMC”


Huawei Ascend AI chip./Huawei

Huawei Ascend AI chip./Huawei
It has been reported that Huawei is providing full support to China's largest foundry (semiconductor contract manufacturing) SMIC for the successful mass production of the 5㎚ (nanometer, one billionth of a meter) process scheduled for operation next year. As the advanced processes of TSMC and Samsung Electronics cannot be utilized due to US regulations, it seems that Huawei is tightening the reins on cooperation such as equipment development so that SMIC, a domestic company, can stabilize the 5㎚ process.

According to industry sources on the 1st, SMIC plans to start operating the foundry 5㎚ process next year. SMIC plans to complete the mass production line by introducing the equipment necessary for mass production of the 5㎚ process as early as this year. SMIC, like Huawei, is subject to US regulations, and imports of ASML's extreme ultraviolet (EUV) exposure equipment, a key facility for processes below 7㎚, are restricted, making it difficult to develop advanced processes.

◇ Huawei's latest AI accelerator manufactured with SMIC 7nm

Huawei recently unveiled the AI accelerator Ascend 910C. The Ascend 910C is an AI accelerator specialized in inference, and has been evaluated to surpass Nvidia's advanced AI accelerator H100 in inference performance. The Ascend 910C will be used by Chinese IT companies, including DeepSec, to develop AI models. The Ascend 910C is known to have been mass-produced using SMIC's 7nm process.

There is a prevailing view that Huawei's mass production of next-generation AI chips will be hindered as SMIC's advanced process is still at the 7㎚ level. Currently, Nvidia, AMD, Intel, etc. are manufacturing AI chips using TSMC's advanced process of 3㎚ or less, so in order to compete with them, it is essential to apply a fine process that can improve chip performance.

To this end, Huawei is understood to be risking its life to ensure smooth mass production of the 5㎚ process of SMIC, a domestic foundry company. Chinese semiconductor equipment company 'SciCarrier', known to be developing equipment in cooperation with Huawei, unveiled a number of equipment solutions applicable to fine processes at SEMICON China 2025 last week. The company is known to have registered a patent for a deep ultraviolet (DUV) equipment process that can replace EUV exposure equipment in the 5㎚ process . In addition, Huawei is said to be strengthening cooperation with SMIC, such as process optimization, so that it can maximize the performance of its chips.

The Hong Kong South China Morning Post (SCMP) reported that “Psycarrier registered a patent two years ago to manufacture 5nm semiconductors using DUV equipment. This is also related to SMIC using DUV to manufacture Huawei’s application processor (AP) using a 7nm process.”

일러스트=챗GPT 달리3


◇ SMIC 5㎚ yield around 30%… “Factory price will be 50% more expensive than TSMC”

The problem is that when using DUV equipment, the precision is lower than that of EUV equipment, resulting in lower yields. If DUV is used instead of EUV, there is a disadvantage in that the semiconductor photo paper position must be adjusted and light must be projected multiple times. Normally, when EUV is used in the 5㎚ manufacturing process, the exposure process is repeated once, or at most twice, but when DUV is used instead, it must be repeated at least four times. As the process becomes more complicated, the yield is bound to become unstable, and the performance of the semiconductor is likely to deteriorate.

Park Yoo-ak, a researcher at Kiwoom Securities, said, “SMIC’s 5㎚ process yield is expected to be less than one-third of that,” and “Due to the low yield, the price of the 5㎚ process is also expected to be 50% more expensive than TSMC.” Currently, TSMC’s 5㎚ process yield is over 90%, while SMIC’s 5㎚ process yield is expected to be around 30%.

A semiconductor industry insider said, “The prevailing analysis is that SMIC’s 5㎚ process yield and performance will fall far short of TSMC and Samsung Electronics’ processes,” but added, “If the process stabilizes thanks to domestic semiconductor manufacturing demand and the level of Chinese semiconductor equipment companies improves, they can quickly increase their market share, which poses a threat to competitors.”

 
If the SiCarrier process is used, that would be interesting. The low yield predictions are associated with the (LE)n style of multipatterning. SAQP-based is much simpler but is more fitting for elongated, limited pitch layouts.
 
SMIC has been working on 5nm for years. I did not think it would be a big challenge without EUV but apparently that is not the case. SMIC, UMC, Globalfoundries really make TSMC look good. So how is China going to catch up without EUV?
 
There were reports Ascend 920 is made on a "6nm" by SMIC. If TechInsights can analyze it, we might see their actual current progress or where they're stuck. "6nm" might still be practically the same design rules as TSMC N7. N5 EUV still needed double patterning but the corresponding DUV requirements have not been explored extensively before.
 
Another chip that might be easier to get for analysis -- Huawei's Kirin 9100 is supposed to be a 6nm SMIC chip.

SMIC has been working on 5nm for years. I did not think it would be a big challenge without EUV but apparently that is not the case. SMIC, UMC, Globalfoundries really make TSMC look good. So how is China going to catch up without EUV?

Just build more chips and feed more coal into datacenters than we do :).

I would think you could match 1000 N3 AI accelerators with 1300-1500 N5 AI accelerators when your government subsidizes everything.
 
Seems like there is considerable government and prestige pressure on both SMIC and Huawei to both transition to 5nm for leading edge AI (Ascend) and mobile APs (Mate/Pura Kirins) as well as to ramp up additional lines that include domestic DUV litho. From recent news though, it seems like there are tough challenges ahead - yield, equipment maintenance, new equipment qualification plus 5nm itself.

From SMIC earnings in May

Recent rumblings on Mate 80 / Kirin 9030 still on 7nm, Huawei bringing up their own line in Shenzhen
 
Looks like SMIC 5nm is going to happen. the reported 30% yield at the moment is not an issue (strategic importance from government POV) and it will only get better over time.

what about beyond 5nm? without adv EUV, 3nm (equivalent feature size) is impossible?
 
Looks like SMIC 5nm is going to happen. the reported 30% yield at the moment is not an issue (strategic importance from government POV) and it will only get better over time.

what about beyond 5nm? without adv EUV, 3nm (equivalent feature size) is impossible?

With enough buckets of money, maybe. I think SMIC and even Huawei are a bit caught in the difficult economic space Intel is experiencing - sub-scale wafer demand at the leading edge and constant pressure to stay at the leading edge. Throw in the EUV and other fab equipment embargo and lack of a real foundry ecosystem at the leading edge, and you have significant recurring costs for limited revenue. And inserting domestic equipment has it own costs in terms of ramp-up and yield improvement. One tiny example - It's not like there is ready to go optical proximity correction and mask synthesis software for new litho entrants. And then there ae the limited volumes compared to Apple/TSMC, Samsung and Intel, who all pump through 3-5x as many leading edge logic wafers as Huawei needs with their current smartphone and AI chip sales.
 
Looks like SMIC 5nm is going to happen. the reported 30% yield at the moment is not an issue (strategic importance from government POV) and it will only get better over time.
If this low yield is not an excursion, then it looks like it has been subsidized by the Chinese government for a while. So there has been no incentive for optimization or improvement of the process.
what about beyond 5nm? without adv EUV, 3nm (equivalent feature size) is impossible?
With the subsidy, in principle nothing would be "impossible" it seems.

I discussed a little about SiCarrier's approach applied to 5nm here: https://chentfred.substack.com/p/sicarriers-saqp-class-patterning

In going to 3nm (48 nm gate pitch, 24 nm M2 track pitch), the M2 patterning would stay the same, the fully self-aligned V1 would stay the same, M1 would need four masks for blocks/cuts instead of two. So there would be added mask count, as expected.
 
X90 is still using N+2 7nm confirmed by Techinsight, not 5nm.

And last week a China de-cap team stated that they bought a 910C and find it is using TSMC version chip after tearing down.

Hence above information give me a feeling that SMIC may enter 5nm with small chip size (mobile application) by 2025 end or 2026 beginning, but they still struggle at AI chip (large chip size) manufacturing even with 7nm node.
 
With the subsidy, in principle nothing would be "impossible" it seems.

They have some patents and a strategy, but no operating tools, even at their initial target of 28nm. And not even litho prototypes. But what can you expect for maybe only $15B invested.

Exclusive: SiCarrier - Huawei partner in chips - seeks $2.8 billion in funds, sources say​

By Che Pan, Julie Zhu, Fanny Potkin and Eduardo Baptista
May 13, 20256:09 PM PDTUpdated May 13, 2025

 
They have some patents and a strategy, but no operating tools, even at their initial target of 28nm. And not even litho prototypes. But what can you expect for maybe only $15B invested.

Exclusive: SiCarrier - Huawei partner in chips - seeks $2.8 billion in funds, sources say​

By Che Pan, Julie Zhu, Fanny Potkin and Eduardo Baptista
May 13, 20256:09 PM PDTUpdated May 13, 2025

It hasn't been clear if it's SMIC doing the fabbing for Huawei or Huawei has their own fab. Either way, any subsidy for low yield must go to Huawei, it seems. SiCarrier is just another vying vendor.

Another thought I had on this was that Huawei is prioritizing AI chip development over foundry process development. It is the opposite of Intel under PG. It's no surprise if Huawei continues to use 7nm for its Ascend series. But it's a fair question if it can remain competitive with this strategy.
 
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