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Hi to all
Am simulating one four bit ripple carry adder having four full adders.
In simulation, its taking too much time to respond (literally stopping at the fourth full adder).
When i remove one full adder and connect one half adder its working fine.
Please clarify this to me.
I would simulate an adder in HSPICE to tell me Speed, Current and Power across Process, Voltage and Temperature. Especially if I'm doing a full-custom IC layout to get the ultimate in performance, power and area.
..I would simulate an adder in HSPICE to tell me Speed, Current and Power across Process, Voltage and Temperature. Especially if I'm doing a full-custom IC layout to get the ultimate in performance, power and area.
Wouldn't argue with the requirement but I'd probably just do a Verilog-AMS behavioral model that matches the single full adder and then build the bigger circuit out of that for faster simulation of the full design.
The behavior of a block (like the adder) is very constrained so full transistor level Spice is overkill. The piece that changes as a design progresses is the wiring, the standard cells don't. So as far as I can tell the only reason for dropping to full Spice is that there isn't a back-annotation methodology for the behavioral model approach.
Dear Daniel,
I am sure there is no netlist problem.
If any transition problem, then it mayn't work in the case [Half adder followed by three full adder].
When i remove my last fulladder, the operation was good.
Earlier my design is a combination of all logic gates now realized using the NOR gates only.
its working fine.
Don't know what the mistake with my earlier design.
Regards
SRINI
I'm quite confused - and it looks as if at least some of your other respondents may be in the same position
Is this a single adder that you are incrementally increasing from one bit to four bits?
or
Is this four times four-bit adders?
When you say that "in simulation it is stopping at the fourth full adder", do you mean
That the simulation does not run when you add the fourth full adder?
or
That the fourth full adder fails to add?
If the problem is that the simulation does not run, how many clock cycles does it take before the simulation stops?
If the problem is that the adder fails to work, have you tried to see what happens when you reduce the clock frequency (extend the times between driven transitions)?
This is the classic problem that I first ran into in 1980.
You are simulating a circuit that has many multi-stable points.
(i.e. circuits that are crossing switching points, but have feedback to latch them into a state)
But simulators ( hspice, spectre, etc. ) are attempting to solve your simulation with a very narrow view.
At each point in the time domain simulation, the simulator will (try to )predict the voltage at the next time step.
(it does so, by using an impedance/reluctance matrix of the circuit and a sytematic guess at then new voltage)
Each guess is checked against a tolerance matrix of error and if the error is small enough, the simulation will procede to the next step.
But when you have an ill-conditioned matrix (i.e. at a bistable simulation point) then the simulator will need to take smaller and smaller steps.
At these bistable points, you can run into a situation where the smallest steps will not be able to predict the voltage at the next timestep.
(Spectre has a shooting method which can sometimes help here ... with a potential loss of accuracy)
