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How Many Wafers Did Intel Produce in 2024

hist78

hist78

Well-known member
My assumptions and method:
  1. 1. Server outsourcing volume – Assume Intel has very limited outsourcing of server products.

  3. 2. Wafer outsourcing ratio – Intel CFO David Zinsner stated that Intel’s goal is to keep no more than 30% of wafer needs outsourced. Since Intel did not publish exact outsourcing figures for 2024, I assume the rate was 15%.

  5. 2. Server configuration – While many servers may use a single CPU, I calculated based on 2 CPUs per server to provide the largest and most favorable quantity estimate for Intel.

  7. 3. Market share – Intel and AMD’s market shares, as well as the overall x86 server share, were taken from various news reports. These numbers may be somewhat high or low, but I intentionally selected values favorable to Intel to produce a best case scenario estimate.

  9. 4. Die per wafer estimates – Intel manufactures many different processors, varying in die size and packaging technologies (chiplets vs. monolithic). The dies per wafer figures I used are rough estimates, leaning toward assumptions that increase Intel’s possible wafer produced.

Conclusion:

I multiplied the 0.65 million 12-inch wafers by 2 to arrive at 1.3 million wafers. This should mostly account for the quantities I underestimated or didn’t include in the calculation.

My estimate for Intel’s total wafer production in 2024 is between 0.65 million and 1.3 million 12-inch wafers, under the best assumptions for Intel.

In comparison, TSMC produced 12.9 million 12-inch–equivalent wafers (published in TSMC 2024 Annual Report) across its 6, 8, and 12-inch fabs in 2024, with the majority being 12-inch. This means Intel’s wafer output volume is far smaller than TSMC’s. TSMC’s 12-inch wafer output is probably 6 to 8 times greater, or even more, than Intel’s.

Please feel free to adjust it using your own numbers or by changing the calculation methods. I look forward to your comments.


1755535390209.png
 
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siliconbruh999 said:
Intel US Fabs produced 1 Million wafers that's not counting Israel and Ireland View attachment 3511

Click to expand...

If we assume that Intel’s Ireland and Israel fabs produced wafer volumes equal to about 30% of Intel’s US fabs, then Intel’s total worldwide wafer output in 2024 will be around 1.3 million 12-inch wafers, which is matching the high end of my estimate.

If we change the ratio to 50%, Intel’s total worldwide wafer output in 2024 would be around 1.5 million 12-inch wafers.

If we change the ratio to 100%, Intel’s total worldwide wafer output in 2024 would be around 2 million 12-inch wafers.

In comparison, TSMC’s 2024 output was 12.9 million 12-inch–equivalent wafers, with a total capacity of 17 million 12-inch–equivalent wafers across all TSMC facilities.

Source: https://investor.tsmc.com/sites/ir/annual-report/2024/2024 Annual Report_E.pdf
 
Here is what ChatGPT 5.0 says:

Here’s a transparent, back-of-the-envelope estimate of Intel’s 2024 wafer starts (300 mm-equivalent, logic) based on public shipment data plus explicit assumptions. Intel doesn’t publish a total wafer count; this builds from PC/server CPU units and then adds a margin for chipsets, networking, PSG/Altera, test wafers, etc. (all noted below).

Bottom line (range with a central estimate)​

  • Estimated 2024 Intel wafer starts: ~0.6M to ~1.6M 300 mm wafers
  • Central estimate: ~1.0M 300 mm wafers
Why this range: PCs shipped in 2024 were ~245–263M units depending on firm (Gartner/IDC/Canalys), with Intel holding ~75% of client CPU units exiting 2024. Server CPU shipments for Intel were ~3.5–4.1M per quarter in 2024 (Mercury Research data cited in coverage), implying the mid-teens of millions for the year. Nearly all “core products” were on 300 mm wafers in 2024. TECHx Mediacrnasia.comCanalysTom's HardwareThe Next PlatformIntel

How the estimate is built (with explicit knobs)​

1) Client CPUs (PCs)​

  • PC units 2024: 245.3M (Gartner) to 262.7M (IDC) to 256.0M (Canalys). TECHx Mediacrnasia.comCanalys
  • Intel’s unit share: use ~75% (Mercury Research, Q4’24). Tom's Hardware
  • Die size / yield (assumptions, mix of desktop “Intel 7” monoliths and some Meteor/Lunar tiles):
    • Low wafers: smaller avg die (≈140 mm²), high yield (≈92%).
    • Mid: ≈180 mm² @ 85% yield.
    • High wafers: larger avg die (≈220 mm²), 80% yield.
    • Note on tiles: some client parts in 2024 used chiplets where not all tiles were Intel-fabbed (e.g., Meteor Lake/Lunar Lake include TSMC-fabbed tiles). This estimate implicitly captures that uncertainty via the die/yield range. WccftechTom's Hardware
Resulting client wafer starts (300 mm-eq):
  • Low: ~0.41M
  • Mid: ~0.64M
  • High: ~0.91M

2) Server CPUs​

  • Observed datapoint: Intel shipped ~4.09M x86 server CPUs in Q3’24 (Mercury Research via NextPlatform), with ~3.46M in Q1’24; annualizing gives low-to-mid teens of millions for 2024. The Next Platform
  • Units (assumptions): Low 12M, Mid 15.5M, High 20M server CPUs for 2024.
  • Die size / yield (assumptions, Sapphire/Emerald heavy):
    • Low: ~350 mm² @ 78%
    • Mid: ~400 mm² @ 70%
    • High: ~600 mm² @ 60%
      (Server dies vary widely; the range spans monolithic and larger chiplet tiles.)
Resulting server wafer starts:
  • Low: ~0.085M
  • Mid: ~0.139M
  • High: ~0.314M

3) Everything else (uplift factor)​

To account for chipsets, Ethernet/NICs, NEX parts, PSG/Altera, management dice, test/monitor wafers, scrap, etc., apply an uplift to CPU-driven wafer demand:
  • Low +15%, Mid +25%, High +30%.

1755547834544.png

Key assumptions you can tune​

  • PC base & Intel share: We used 245–263M PCs and ~75% Intel share; nudging either by ±5 pp moves client wafers by ~±50–80k. TECHx Mediacrnasia.comCanalysTom's Hardware

  • Die size & yields: Biggest swing factor. If 2024 skewed more to larger monolithic desktop dice (Intel 7), numbers move toward the high scenario; more small mobile tiles and better yields push toward low.

  • Tile sourcing mix: 2024 client ramp included Meteor/Lunar tiles, some fabbed at TSMC (not Intel); we modeled uncertainty via the wide die/yield range rather than trying to net out tile-by-tile, which isn’t publicly disclosed per unit mix. WccftechTom's Hardware

  • “Other silicon” uplift: 15–30% is a typical heuristic for Intel’s non-CPU silicon and operational wafers; if you set this to +20%, the mid case lands just over ~1.0M.

Sanity checks​

  • Intel states that as of end-2024, core products were on 300 mm wafers, with the majority on Intel 7 while Intel 4/3 ramped (consistent with our die/yield choices). Intel

  • The mid case (~1.0M wafers/year) is far smaller than a pure-play foundry like TSMC (multi-million 300 mm wafers per year) but reasonable for an IDM focused on its own CPUs plus a nascent foundry business. (Intel also set up a Fab 34 JV to secure long-term wafer capacity—evidence of scaling plans rather than current output.) Newsroom
If you want, I can adjust the model to your preferred inputs (e.g., set specific client/server mixes, die sizes per SKU family, or a different “other” uplift) and give you a tighter band for 2024—or roll the same method forward for 2025 guidance using current run-rates.
 
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Conclusion: Dan + SemiWiki + ChatGPT eliminate hundreds of Wall Street semi industry analysts' jobs!

Dan, I think POTUS should demand 15% of Wall Street's semi analysts' salaries and donate it to Dan, to be used for the benefit of SemiWiki's participants, at least a free Mac for everyone!!

PS of course, what company will sell what kind of Mac ( ;) ?!) to Dan may depend slightly on the size of the semi analysts' salaries and hopefully a couple of those 1.4 M SemiWiki participants will voluntarily retire now to Florida, knowing that Dan has all under control regarding the semi-industry.....
 
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MKWVentures said:
Does Chat GPT know where the Altera and Chipset and Networking parts are made?
Click to expand...

A) Intel-fabbed families (current flagships)​

Stratix 10 (GX/SX/MX/TX)​

  • Process: Intel 14 nm Tri-Gate (“Intel 14 nm”). Intel CDRDIntel Download Center

  • Likely wafer fabs: Intel’s 14 nm/10 nm-capable sites: Arizona (Ocotillo), Oregon (Ronler—development + some HVM), Ireland (Leixlip), Israel (Kiryat Gat). Intel does not map each SKU to a site publicly. IntelIntel Download CenterIntel

Agilex 7 (F-/I-/M-series)​

  • Process: Primarily Intel 10 nm SuperFin; some materials note Intel 7 is also used in certain Agilex 7 variants (chiplet/SIP combos with EMIB). altera.comIntelIntel CDRD

  • Likely wafer fabs: Intel’s 10 nm/Intel 7 fabs in Israel, Oregon, Arizona (10 nm ramp historically in OR+IL; ARIZ added later) and Intel 7 in AZ/IL. Again, Altera/Intel don’t publish per-SKU site maps. Tom's HardwareIntel

Agilex 5 (D-/E-series)​

  • Process: Intel 7 (successor to 10 nm Enhanced SuperFin). altera.comIntel CDRD
  • Likely wafer fabs: Intel 7 HVM at Arizona and Israel. Intel
Note on “where exactly”: Intel runs a “single virtual factory” model and does not list which Altera P/N comes from which fab. The public footprint shows where those nodes run in volume; that constrains the plausible sites. Intel
Click to expand...

B) TSMC-fabbed families (legacy & cost-optimized)​

Stratix V / Arria V / Cyclone V​

  • Process: TSMC 28 nm (HP for Stratix V; LP for Cyclone/Arria variants). TSMC
  • Stated explicitly for Cyclone V: “Built on TSMC’s 28 nm LP.” altera.comIntel CDRDDigiKey

MAX 10​

Packaging note (not wafers, but often asked)​


After wafer fabrication, Altera devices are assembled/tested across Intel’s and partners’ assembly & test footprint—Malaysia, Vietnam, Costa Rica, Chengdu (China), plus New Mexico (advanced packaging) for EMIB/3D work. Wafer fab location ≠ package/test location. Intel Download Center


Forward-looking​

Altera has stated intent to migrate future high-end FPGAs to Intel 18A nodes, aligning more of the portfolio with Intel’s leading-edge internal fabs as they come online (Ireland, Arizona; Europe later). Timing and specific families will be announced product-by-product. EENews Europe

Bottom line​

  • If you’re buying Stratix 10 / Agilex 7 / Agilex 5, the wafers are made at Intel fabs on Intel nodes (14 nm, 10 nm SuperFin, Intel 7).
  • If you’re buying MAX 10 / Cyclone V / Arria V / Stratix V, the wafers are made at TSMC (55 nm eFlash; 28 nm LP/HP).
  • Intel/Altera don’t disclose the specific fab per SKU, but Intel’s published node-to-site footprint constrains the geography (U.S., Ireland, Israel for these nodes). IntelIntel Download Center

If you tell me the exact family/SKU, I can map it to the process and the most likely wafer site, and flag any packaging (e.g., EMIB + HBM) implications.
 
IMO, with such a relatively small in-house wafer output volume, moving 10% or 15% of outsourced advanced logic back to Intel doesn’t make a huge difference. At the same time, it may deprive Intel’s product division of the ability to compete. This is probably why Intel has been considering outsourcing up to 30% of its wafer needs to external foundries.
 
hist78 said:
IMO, with such a relatively small in-house wafer output volume, moving 10% or 15% of outsourced advanced logic back to Intel doesn’t make a huge difference. At the same time, it may deprive Intel’s product division of the ability to compete. This is probably why Intel has been considering outsourcing up to 30% of its wafer needs to external foundries.
Click to expand...

Do you think Intel Product Division can compete with AMD and Nvidia using the same TSMC process? Remember, Jensen Huang and Lisa Su are both Taiwanese and are good friends with CC Wei. Even worse, Pat Gelsinger had an adversarial relationship with TSMC which is a very bad thing. Maybe Lip-Bu can fix that? If not I do not think Intel Products will be competitive on TSMC processes. Just my opinion of course.
 
Daniel Nenni said:
Do you think Intel Product Division can compete with AMD and Nvidia using the same TSMC process? Remember, Jensen Huang and Lisa Su are both Taiwanese and are good friends with CC Wei. Even worse, Pat Gelsinger had an adversarial relationship with TSMC which is a very bad thing. Maybe Lip-Bu can fix that? If not I do think Intel Products will be competitive on TSMC processes. Just my opinion of course.
Click to expand...

Intel and TSMC have shared a long and cordial relationship. Intel’s founders, Gordon Moore and Robert Noyce, were friends with TSMC’s founders since their 30s. Morris Chang fondly recalled those days when they attended IEDM conferences, went out for dinner and drinks afterward, and walked back to the hotel in the light snow, singing along the way.

When Morris Chang was seeking founding investors to start TSMC, Intel was one of the companies he approached. The person who lead the evaluation of Chang’s proposal was Craig Barrett, then a senior vice president (and later Intel’s CEO and Chairman). Although Intel ultimately declined to invest in TSMC’s founding in 1987, it placed orders with the nascent startup a year later in 1988, after Andy Grove’s site visit and TSMC’s resolution of more than 100 issues based on Intel’s recommendations. In fact, Intel became TSMC’s first major customer with a strong worldwide reputation. Soon after, Philips, Texas Instruments, and Motorola also joined TSMC’s customer list.

Many years later when Paul Otellini was Intel’s CEO, Morris Chang asked him to recommend a candidate for TSMC’s board. Otellini suggested Craig Barrett, who was about to retire as Intel’s Chairman. In the end, however, Barrett declined TSMC’s invitation.

This long-standing relationship began to deteriorate when Pat Gelsinger returned to Intel as CEO in 2021 and launched a series of attacks against TSMC.

I believe Mr. Li-Pu Tan is capable of rebuilding this long standing relationship between Intel and TSMC. If there are ten reasons for Intel and TSMC to see each other as rivals, there are a hundred reasons for them to be partners and help each other.
 
KevinK said:
@hist78 ,
What are you trying to do with the numbers ? We used to track wafer capacity across all the foundries at leading edge digital processes (leading 3 nodes) using Semi's database of fabs.


It was interesting over the years to watch TSMC catch up, then surpass Intel in leading edge digital volume, without any apparent sense of urgency on Intel's part.
Click to expand...

By estimating Intel’s wafer output volume, I am trying to better understand the company’s capacity and capability in today’s fabless/foundry environment. I knew that Intel was facing serious financial, technology, product, and production challenges, but I was still surprised to find that its wafer output volume is relatively small. This certainly wasn’t because Intel lacked the money to invest in itself, between 2010 and Q1 2021, Intel spent $83.54 billion on share buybacks alone.

Somehow, Intel forgot to invest that precious cash into its own future.
 
user nl said:
Conclusion: Dan + SemiWiki + ChatGPT eliminate hundreds of Wall Street semi industry analysts' jobs!

Dan, I think POTUS should demand 15% of Wall Street's semi analysts' salaries and donate it to Dan, to be used for the benefit of SemiWiki's participants, at least a free Mac for everyone!!

PS of course, what company will sell what kind of Mac ( ;) ?!) to Dan may depend slightly on the size of the semi analysts' salaries and hopefully a couple of those 1.4 M SemiWiki participants will voluntarily retire now to Florida, knowing that Dan has all under control regarding the semi-industry.....
Click to expand...
Not Mac but Intel CPU made in Intel fabs to support IFS
 
hist78 said:
IMO, with such a relatively small in-house wafer output volume, moving 10% or 15% of outsourced advanced logic back to Intel doesn’t make a huge difference. At the same time, it may deprive Intel’s product division of the ability to compete. This is probably why Intel has been considering outsourcing up to 30% of its wafer needs to external foundries.
Click to expand...
But it's only 30%, isn't it?
Not all
At least you can use it properly depending on the purpose
I don't think going back to the company is the reason why it will be less profitable.
 
Daniel Nenni said:
Do you think Intel Product Division can compete with AMD and Nvidia using the same TSMC process? Remember, Jensen Huang and Lisa Su are both Taiwanese and are good friends with CC Wei. Even worse, Pat Gelsinger had an adversarial relationship with TSMC which is a very bad thing. Maybe Lip-Bu can fix that? If not I do think Intel Products will be competitive on TSMC processes. Just my opinion of course.
Click to expand...
But Intel manufacturing is not a competitive advantage. It is and has been a disadavantage that why Product group pushed very hard for outsourcing. They want ability to work with the best supplier with flexibility.
 
hist78 said:
Wow, my estimate is 0.65M to 1.3M. It’s so close to ChatGPT-5 AI’s result! I can go to McDonald’s tonight to celebrate my humble achievement!
Click to expand...

INTEL processed 1 M wafers in 2024, mostly on INTEL 7 and 10, according to all the estimates in this thread and INTEL's own reporting. INTEL Foundry had 17.5 B US$ revenue in 2024.
https://www.intc.com/news-events/pr...s-fourth-quarter-and-full-year-2024-financial

So INTEL's 7/10 wafers cost 17500 US$/wafer
(for the ease of arguments we include the relatively small IFS packaging revenue in here).

TSMC processed some 10 M wafers in 2024 on total revenue of some 88 B US$.
TSMC's wafer costs are given/estimated here:
https://wccftech.com/tsmc-3nm-wafer...crease-over-5nm-next-gen-cpus-gpus-expensive/
1755755330582.png


TSMC's gross margin in 2024 is 56%. For the last decade or so, TSMC's gross margin has ranged between some 43-56%.

INTEL stated it will not do any new projects that have less than 50% gross margin.
https://www.tomshardware.com/tech-i...ust-deliver-50-percent-to-get-the-green-light

So, how will / why would INTEL3.0-Foundry Services ramp 18A and 14A the coming 3-5 years if they cannot provide 50% gross margin?

So, why would any leading-edge big fabless customer move to INTEL Foundry Services in 2028-2030?
 
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user nl said:
Perhaps POTUS will make sure that also hist78's BIG Macs will be made at IFS after the USG's cash infusion and SoftBank's "seal of approval (like they gave to WeWork!)". IFS will certainly be leading TSMC then in this novel process node and Make America BIG Again !
Click to expand...
Ironically, big MACs (multiplier accumulator AI chips) are precisely what IFS needs to be producing ...
 
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