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How Many Wafers Did Intel Produce in 2024

hist78

hist78

Well-known member
My assumptions and method:
  1. 1. Server outsourcing volume – Assume Intel has very limited outsourcing of server products.

  3. 2. Wafer outsourcing ratio – Intel CFO David Zinsner stated that Intel’s goal is to keep no more than 30% of wafer needs outsourced. Since Intel did not publish exact outsourcing figures for 2024, I assume the rate was 15%.

  5. 2. Server configuration – While many servers may use a single CPU, I calculated based on 2 CPUs per server to provide the largest and most favorable quantity estimate for Intel.

  7. 3. Market share – Intel and AMD’s market shares, as well as the overall x86 server share, were taken from various news reports. These numbers may be somewhat high or low, but I intentionally selected values favorable to Intel to produce a best case scenario estimate.

  9. 4. Die per wafer estimates – Intel manufactures many different processors, varying in die size and packaging technologies (chiplets vs. monolithic). The dies per wafer figures I used are rough estimates, leaning toward assumptions that increase Intel’s possible wafer produced.

Conclusion:

I multiplied the 0.65 million 12-inch wafers by 2 to arrive at 1.3 million wafers. This should mostly account for the quantities I underestimated or didn’t include in the calculation.

My estimate for Intel’s total wafer production in 2024 is between 0.65 million and 1.3 million 12-inch wafers, under the best assumptions for Intel.

In comparison, TSMC produced 12.9 million 12-inch–equivalent wafers (published in TSMC 2024 Annual Report) across its 6, 8, and 12-inch fabs in 2024, with the majority being 12-inch. This means Intel’s wafer output volume is far smaller than TSMC’s. TSMC’s 12-inch wafer output is probably 6 to 8 times greater, or even more, than Intel’s.

Please feel free to adjust it using your own numbers or by changing the calculation methods. I look forward to your comments.


1755535390209.png
 
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siliconbruh999 said:
Intel US Fabs produced 1 Million wafers that's not counting Israel and Ireland View attachment 3511

Click to expand...

If we assume that Intel’s Ireland and Israel fabs produced wafer volumes equal to about 30% of Intel’s US fabs, then Intel’s total worldwide wafer output in 2024 will be around 1.3 million 12-inch wafers, which is matching the high end of my estimate.

If we change the ratio to 50%, Intel’s total worldwide wafer output in 2024 would be around 1.5 million 12-inch wafers.

If we change the ratio to 100%, Intel’s total worldwide wafer output in 2024 would be around 2 million 12-inch wafers.

In comparison, TSMC’s 2024 output was 12.9 million 12-inch–equivalent wafers, with a total capacity of 17 million 12-inch–equivalent wafers across all TSMC facilities.

Source: https://investor.tsmc.com/sites/ir/annual-report/2024/2024 Annual Report_E.pdf
 
Here is what ChatGPT 5.0 says:

Here’s a transparent, back-of-the-envelope estimate of Intel’s 2024 wafer starts (300 mm-equivalent, logic) based on public shipment data plus explicit assumptions. Intel doesn’t publish a total wafer count; this builds from PC/server CPU units and then adds a margin for chipsets, networking, PSG/Altera, test wafers, etc. (all noted below).

Bottom line (range with a central estimate)​

  • Estimated 2024 Intel wafer starts: ~0.6M to ~1.6M 300 mm wafers
  • Central estimate: ~1.0M 300 mm wafers
Why this range: PCs shipped in 2024 were ~245–263M units depending on firm (Gartner/IDC/Canalys), with Intel holding ~75% of client CPU units exiting 2024. Server CPU shipments for Intel were ~3.5–4.1M per quarter in 2024 (Mercury Research data cited in coverage), implying the mid-teens of millions for the year. Nearly all “core products” were on 300 mm wafers in 2024. TECHx Mediacrnasia.comCanalysTom's HardwareThe Next PlatformIntel

How the estimate is built (with explicit knobs)​

1) Client CPUs (PCs)​

  • PC units 2024: 245.3M (Gartner) to 262.7M (IDC) to 256.0M (Canalys). TECHx Mediacrnasia.comCanalys
  • Intel’s unit share: use ~75% (Mercury Research, Q4’24). Tom's Hardware
  • Die size / yield (assumptions, mix of desktop “Intel 7” monoliths and some Meteor/Lunar tiles):
    • Low wafers: smaller avg die (≈140 mm²), high yield (≈92%).
    • Mid: ≈180 mm² @ 85% yield.
    • High wafers: larger avg die (≈220 mm²), 80% yield.
    • Note on tiles: some client parts in 2024 used chiplets where not all tiles were Intel-fabbed (e.g., Meteor Lake/Lunar Lake include TSMC-fabbed tiles). This estimate implicitly captures that uncertainty via the die/yield range. WccftechTom's Hardware
Resulting client wafer starts (300 mm-eq):
  • Low: ~0.41M
  • Mid: ~0.64M
  • High: ~0.91M

2) Server CPUs​

  • Observed datapoint: Intel shipped ~4.09M x86 server CPUs in Q3’24 (Mercury Research via NextPlatform), with ~3.46M in Q1’24; annualizing gives low-to-mid teens of millions for 2024. The Next Platform
  • Units (assumptions): Low 12M, Mid 15.5M, High 20M server CPUs for 2024.
  • Die size / yield (assumptions, Sapphire/Emerald heavy):
    • Low: ~350 mm² @ 78%
    • Mid: ~400 mm² @ 70%
    • High: ~600 mm² @ 60%
      (Server dies vary widely; the range spans monolithic and larger chiplet tiles.)
Resulting server wafer starts:
  • Low: ~0.085M
  • Mid: ~0.139M
  • High: ~0.314M

3) Everything else (uplift factor)​

To account for chipsets, Ethernet/NICs, NEX parts, PSG/Altera, management dice, test/monitor wafers, scrap, etc., apply an uplift to CPU-driven wafer demand:
  • Low +15%, Mid +25%, High +30%.

1755547834544.png

Key assumptions you can tune​

  • PC base & Intel share: We used 245–263M PCs and ~75% Intel share; nudging either by ±5 pp moves client wafers by ~±50–80k. TECHx Mediacrnasia.comCanalysTom's Hardware

  • Die size & yields: Biggest swing factor. If 2024 skewed more to larger monolithic desktop dice (Intel 7), numbers move toward the high scenario; more small mobile tiles and better yields push toward low.

  • Tile sourcing mix: 2024 client ramp included Meteor/Lunar tiles, some fabbed at TSMC (not Intel); we modeled uncertainty via the wide die/yield range rather than trying to net out tile-by-tile, which isn’t publicly disclosed per unit mix. WccftechTom's Hardware

  • “Other silicon” uplift: 15–30% is a typical heuristic for Intel’s non-CPU silicon and operational wafers; if you set this to +20%, the mid case lands just over ~1.0M.

Sanity checks​

  • Intel states that as of end-2024, core products were on 300 mm wafers, with the majority on Intel 7 while Intel 4/3 ramped (consistent with our die/yield choices). Intel

  • The mid case (~1.0M wafers/year) is far smaller than a pure-play foundry like TSMC (multi-million 300 mm wafers per year) but reasonable for an IDM focused on its own CPUs plus a nascent foundry business. (Intel also set up a Fab 34 JV to secure long-term wafer capacity—evidence of scaling plans rather than current output.) Newsroom
If you want, I can adjust the model to your preferred inputs (e.g., set specific client/server mixes, die sizes per SKU family, or a different “other” uplift) and give you a tighter band for 2024—or roll the same method forward for 2025 guidance using current run-rates.
 
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MKWVentures said:
Does Chat GPT know where the Altera and Chipset and Networking parts are made?
Click to expand...

A) Intel-fabbed families (current flagships)​

Stratix 10 (GX/SX/MX/TX)​

  • Process: Intel 14 nm Tri-Gate (“Intel 14 nm”). Intel CDRDIntel Download Center

  • Likely wafer fabs: Intel’s 14 nm/10 nm-capable sites: Arizona (Ocotillo), Oregon (Ronler—development + some HVM), Ireland (Leixlip), Israel (Kiryat Gat). Intel does not map each SKU to a site publicly. IntelIntel Download CenterIntel

Agilex 7 (F-/I-/M-series)​

  • Process: Primarily Intel 10 nm SuperFin; some materials note Intel 7 is also used in certain Agilex 7 variants (chiplet/SIP combos with EMIB). altera.comIntelIntel CDRD

  • Likely wafer fabs: Intel’s 10 nm/Intel 7 fabs in Israel, Oregon, Arizona (10 nm ramp historically in OR+IL; ARIZ added later) and Intel 7 in AZ/IL. Again, Altera/Intel don’t publish per-SKU site maps. Tom's HardwareIntel

Agilex 5 (D-/E-series)​

  • Process: Intel 7 (successor to 10 nm Enhanced SuperFin). altera.comIntel CDRD
  • Likely wafer fabs: Intel 7 HVM at Arizona and Israel. Intel
Note on “where exactly”: Intel runs a “single virtual factory” model and does not list which Altera P/N comes from which fab. The public footprint shows where those nodes run in volume; that constrains the plausible sites. Intel
Click to expand...

B) TSMC-fabbed families (legacy & cost-optimized)​

Stratix V / Arria V / Cyclone V​

  • Process: TSMC 28 nm (HP for Stratix V; LP for Cyclone/Arria variants). TSMC
  • Stated explicitly for Cyclone V: “Built on TSMC’s 28 nm LP.” altera.comIntel CDRDDigiKey

MAX 10​

Packaging note (not wafers, but often asked)​


After wafer fabrication, Altera devices are assembled/tested across Intel’s and partners’ assembly & test footprint—Malaysia, Vietnam, Costa Rica, Chengdu (China), plus New Mexico (advanced packaging) for EMIB/3D work. Wafer fab location ≠ package/test location. Intel Download Center


Forward-looking​

Altera has stated intent to migrate future high-end FPGAs to Intel 18A nodes, aligning more of the portfolio with Intel’s leading-edge internal fabs as they come online (Ireland, Arizona; Europe later). Timing and specific families will be announced product-by-product. EENews Europe

Bottom line​

  • If you’re buying Stratix 10 / Agilex 7 / Agilex 5, the wafers are made at Intel fabs on Intel nodes (14 nm, 10 nm SuperFin, Intel 7).
  • If you’re buying MAX 10 / Cyclone V / Arria V / Stratix V, the wafers are made at TSMC (55 nm eFlash; 28 nm LP/HP).
  • Intel/Altera don’t disclose the specific fab per SKU, but Intel’s published node-to-site footprint constrains the geography (U.S., Ireland, Israel for these nodes). IntelIntel Download Center

If you tell me the exact family/SKU, I can map it to the process and the most likely wafer site, and flag any packaging (e.g., EMIB + HBM) implications.
 
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