I am beginner in TANNER (Analog design). How we Know How much Technology (L) best suit for my design in TANNER and How i calculate or find the value, as its done only simulation, which is not the part of Hardware realization...Is it takes any random value (proceed to lower one, e.g. 20nm)
How I Know How much Technology (L) best suit for my design in TANNER
- Thread starter Kalyan
- Start date
Daniel Payne
Moderator
When you talk about L, do you mean the channel length of an MOS transistor? If so, then what you typically do is review your chip design requirements, locate the highest performance block in the chip, create a preliminary schematic and netlist, then simulate it in SPICE. If you can meet the speed, power and area requirements at that process node, then you have success. If you don't meed the specifications, then try another process node.
A power management IC may be typically designed with 180nm process technology, while the latest Apple A7 processor is designed in 28nm process technology. It all depends on the type of chip that you need to design.
A power management IC may be typically designed with 180nm process technology, while the latest Apple A7 processor is designed in 28nm process technology. It all depends on the type of chip that you need to design.
Marc Murphy
New member
Hi Kaylan, it sounds like you are trying to figure out which MOSFET minimum length to use to do some practice design with Tanner tools.
Generally you pick the min. L (of the technology) based on performance and cost constraints. As Daniel mentions, power management ICs will work with 180nm technology... not super expensive or fast. The Apple A7 uses 28 nm technology... much more expensive but required for performance reasons.
NC State has some free Cadence design kits that you may be able to port to use with the Tanner EDA suite.
NCSU CDK - NCSU EDA Wiki
If you're in school maybe your local EDA expert can help you get started. You don't typically make up your own transistor models. You use the models that come with your chosen process.
Generally you pick the min. L (of the technology) based on performance and cost constraints. As Daniel mentions, power management ICs will work with 180nm technology... not super expensive or fast. The Apple A7 uses 28 nm technology... much more expensive but required for performance reasons.
NC State has some free Cadence design kits that you may be able to port to use with the Tanner EDA suite.
NCSU CDK - NCSU EDA Wiki
If you're in school maybe your local EDA expert can help you get started. You don't typically make up your own transistor models. You use the models that come with your chosen process.