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Do the overall "performance" benefits from Backside Power Delivery decrease (or increase?) when moving from single height ("2D") lithography to 3D stacked? (What are the physics involved?)
Are you asking about die-to-die stacking (face-to-face, face-to-back), chiplets in vertical integration, or high-bandwidth memory (HMB) stacked atop logic?
Are you asking about die-to-die stacking (face-to-face, face-to-back), chiplets in vertical integration, or high-bandwidth memory (HMB) stacked atop logic?
"Yes" But I'm most curious about 3D stacking of logic on top of logic. Do the benefits of BSPD decrease or perhaps increase vs. non-BSPD fabrication vs. non-stacked logic.
But I'm most curious about 3D stacking of logic on top of logic. Do the benefits of BSPD decrease or perhaps increase vs. non-BSPD fabrication vs. non-stacked logic.