Nonsense.
Here you go again. How are design environments with and without internal fabrication different?
Former Intel Board members call for breakup
- Thread starter osnium
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And you still haven't answered any of my questions.
delong.height
Active member
The one on Arrow lake clearly illustrate the point that Intel design team can no longer use manufacturing as an excuse. They are using TSMC N3B., yet failed to deliver a good score even company to last gen AMD product 7850X3D, and mediocre compare to current gen non-X3D product.
And here is the thing. As an Intel investor here, when they are doing a good job, I feel very proud. But if they aren't, I can speak truthfully. And so far, they hasn't. I don't have to be an engineer to understand how disappoint the professional feels when they are testing the real silicon. I see it from their thumbnails. And they shouldn't have done it this poorly.
The design team must be hold accountable.
Even if Paul O acquired Nvidia. He could do very little to change the upside. There will be Avidia or Ovidia in the market eating Intel's lunch just like what's happening today. There's nothing that could be done, little they can save because they are poor allocators. Every investment they have made over the last 20 years have turned out to be an disaster. This includes every acquistion they did, see mobileye, habana, altera, etc. Hundred of billions of USD worth of stock being repurchased. None actually boost it significantly, because they don't have a proper business model.
Yet, it is worthy to be tried.
They are working with TSMC, and I don't think they need to worry much about internal fabrication constraints. The current gen microarchitecture was designed to be >99% compatible between PDKs.
And here is the thing. As an Intel investor here, when they are doing a good job, I feel very proud. But if they aren't, I can speak truthfully. And so far, they hasn't. I don't have to be an engineer to understand how disappoint the professional feels when they are testing the real silicon. I see it from their thumbnails. And they shouldn't have done it this poorly.
The design team must be hold accountable.
In tech, literally no one should do M&A unless you are going for the market. But if you aren't a good capital allocator, then you shouldn't be thinking of it at all.
Even if Paul O acquired Nvidia. He could do very little to change the upside. There will be Avidia or Ovidia in the market eating Intel's lunch just like what's happening today. There's nothing that could be done, little they can save because they are poor allocators. Every investment they have made over the last 20 years have turned out to be an disaster. This includes every acquistion they did, see mobileye, habana, altera, etc. Hundred of billions of USD worth of stock being repurchased. None actually boost it significantly, because they don't have a proper business model.
And here is the thing. Gelsinger is not wrong, he is paranoid, otherwise they aren't going to go through this difficult path at first place.
Yet, it is worthy to be tried.
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DepthFirst
Member
Before it was certain that spun out Intel Fabs would die shortly on its own. Now after this disastrous AL launch it appears that separated neither company would go anywhere but the dustbin.
Agreed. Intel Design and Intel Manufacturing share a heart, you kill one you kill the other, my opinion.
It will be interesting to hear what Pat G has to say next week.
I really do think Intel has a future outsourcing their manufacturing to other foundries like Tower, UMC, and maybe Samsung. GlobalFoundries could also be an option. They need new nodes. These foundries could also share an ecosystem. Intel needs to fill the fabs they are building and that is one way to do it.
tooLongInEDA
Moderator
Those two statements do seem contradictory.
1) Intel design and manufacturing can't be separated without killing both
2) Intel manufacturing can be outsourced
And how is [partially or wholly] outsourcing manufacturing to "not TMSC" any different (or better) than [partially or wholly] outsourcing to TSMC ?
Perhaps statement 1) is correct. And perhaps that is the problem in a fabless world.
I don't have strong evidence for this*, but we don't know if N3B let Intel hit the frequency targets they were hoping for / expecting with Arrow Lake. 14th gen on Intel 7 can hit 5.7-6 GHz at a lower voltage than Arrow Lake on N3B based on some overclocks I've been looking at. Intel can also sell a processor hitting 6.2 GHz reliably on Intel 7. (Do we know that N3B can offer higher top end frequencies than N4?)
A 10% frequency gain on Arrow Lake would make things look a lot different.
*I'm acknowledging way too many variiables to know for sure: chiplet uarch, new uarch, # of chip revisions, etc.
Intel needs a close connection between design and manufacturing. It matters, which is why TSMC offers first class services to companies that are exclusive to TSMC. Intel has always had that with their design and manufacturing which is why Intel dominated the business for so long. Intel will never have that with TSMC given the history. Without inside manufacturing Intel will be at a disadvantage against AMD and others since AMD flies first class with TSMC.
One strategy would be for Intel to be the manufacturing standard for the NOT TSMC business by leveraging Tower, UMC, GF, and maybe Samsung as fronts. The world needs a viable second source for leading edge semiconductors but competing with TSMC is near impossible alone. Intel could lead a coalition of foundries that could compete with TSMC, there is strength in numbers.
siliconbruh999
Well-known member
Can we please drop the OC frequency cause TSMC can't compete there currently the frequency world records for Nodes
Intel i7 Process：14900KS@9117.8 MHz
TSMC N3B Process：285K@7488.8 MHz
TSMC N4P Process：9950X@7548.7 MHz
TSMC N5P Process：7950X@7472 MHz
even AMD can't beat Intel at Memory sensetive workload without going 3D Vcache
x.com
x.com
Can we please drop the OC frequency cause TSMC can't compete there currently the frequency world records for Nodes
Intel i7 Process：14900KS@9117.8 MHz
TSMC N3B Process：285K@7488.8 MHz
TSMC N4P Process：9950X@7548.7 MHz
TSMC N5P Process：7950X@7472 MHz
even AMD can't beat Intel at Memory sensetive workload without going 3D Vcache
x.com
I wasn't referring to LN2 OCs, but very mild OCs to see if Arrow Lake is really stuck at 5.7 GHz or could go a little higher to 6.0-6.2 GHz like the 14900K and 14900KS are shipping at. It seems that 285K is shipped at it's max stable clock already, so there's no headroom left. To me it just begs the quesiton if they expected higher frequency to cover the areas where 285K loses to the prior gen, and didn't get it with the N3B node.
(BTW on the Record OC side - even Intel 14nm offers higher clocks than any TSMC node - 10900K hits 7.7 GHz, though that's not relevant for Arrow Lake of course).
I'm also academically curious about this stuff as I've always read that at some point future nodes could introduce frequency regressions due to various effects with ever smaller transistors.
siliconbruh999
Well-known member
They are not LN2 but Liquid Helium nothing more satisfying than pushing silicon to the limits
I don't think TSMC Nodes will be better for these scenarios of pushing to highest limits of V/F curve of an Arch like Intel's
I don't think TSMC Nodes will be better for these scenarios of pushing to highest limits of V/F curve of an Arch like Intel's
tooLongInEDA
Moderator
Thanks, that's quite helpful.
However, the next question we probably need to ask is whether leading a coalition of equals is really in Intel's DNA - or a challenge they're capable of rising to. They've never had to operate in that way before (actually sharing stuff as equals). This all looks good in theory, but would it actually work in practice ?
People need to stop with this notion that process performance = Fmax. This has never been true even in the Dennard days. Fmax is a product dependent criteria. Power = Cdyn*V^2*f + leakage. ARL will have inevitably higher power consumption floor from cross die communications and the IOs/uncore being on N6 (so not really any better than intel 7). So that means to hit a given power savings target the CPU die needs an even larger power savings. Well ok your leakage per fet and power-performance characteristics are a alot better on N3. But not so fast. The number of transistors per core is much higher on ARL. If I was a betting man I would say the number of devices is larger than the leakage reduction from i7 -> N3. So your total leakage is up and your Cdyn is way up (from the extra complexity and maybe also just inherently from the tighter transistor packing depending on if TSMC was scaling cap faster or slower than density). Okay there is nothing left to do but lower V, and as a natural consequence of this f also needs to come down to ensure stable operations. Now if you did this exact same die with the same power targets, on i7 your f would have needed to drop more for a given V drop (even if we ignore the leakage component).
So TLDR Fmax is mostly at the hands of designers not the node. A good example is looking at some 16FF-RF thing. N3 is much faster inherently, but if you looked at an Apple A series SOC and some 10 GHz cellular radio you sure as hell wouldn't know it.
With that rant done, to answer your direct question. When a process is young the process is less stable ie less uniform. As you tighten up the process corners you can run the same design faster (I'm not a chip designer, but the vibe I got for why this is the case is that the chip can only be as fastest as the lowest common denominator), tighten up your voltage guardband, etc. You also have fewer transistors sucking up disproportionate amounts of power. So even if TSMC didn't make any direct performance enhancements (ie higher strain, better WFMs/VTs, higher cap MIMs, lower device/BEOL RC) you would still see designers able to make chip level enhancements as TSMC smoothed out the process corners. I suspect this is how you get minor clock speed refreshes@iso-ish power parts (which are presumably using the same process version) like AMD's 3800XT vs 3800X, the 5800X-3D over the 5700X-3D, and intel 13th gen to 14th gen.
You say this as if IM-Flash or Numonyx never existed. Joint manufacturing ventures are something intel has done for years. Even though IM-Flash fell apart I don't get the vibe of this being an intel arrogance moment. Rather they had different technological directions they wanted to go (CT vs FG NAND) because Micron was selling commodity NAND mostly in client and intel was trying to sell data center SSDs to bundle with Xeons. And now that foundry is a thing intel has continued this tradition with collaborations with Tower, UMC, and external OSATs.
But either way I suspect an intel foundry alliance would have intel primarily at the helm given they seem to be the only ones who can reliably bring the heat to Fab12 in Hsinchu, or with the internal volume to fill multiple leading edge logic fabs.
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delong.height
Active member
The key here is Samsung because Intel only need leading edge.
Because building fabs in USA, especially a new one is expensive. It's not worth it based on ROIC (return on invested capital) point of view. Samsung has plenty of capacity that's heavily under utilized.
The key here is that Intel need a better cost structure than TSMC + AMD/NVDA combined, you take either AMD or NVDA, or you average the two's hardware sale, then you add on the TSMC's margin. Intel need to be above that. Only with these criteria can Intel afford to be the leader in not TSMC market. Intel is an IDM, and it will likely never be changed because Arrow lake has proved it, Intel is only the best when it's using the best underlying process node, the design team doesn't matter. It's like how AWS is to Amazon, third party business + advertising to Amazon eCommerce. It significantly enable Amazon to expand its ability to invest into the next big thing. But in order to accomplish that, the core need to be good. Same apply to Intel, if Intel can supply a competitive hardware on a cutting edge process node that compete with a much lower price point while still earning a decent profit margin, that will be a good story to be told.
18A can be outsourced, and that will be good for everybody. For Intel, they can get their product at a much lower cost without spending a ton in overhead, while still earning a lot from the franchisee model. For Samsung, they can still invest into their in-house solution or completely co-develop 14A and beyond. For everybody else in the industry, there is no reason not to use an alternative approach that's available in the marketplace, and perhaps cheaper.
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Thanks for the detail here, that's why I love this forum and the people here. I'll search around for good definitions of measuring process performance.
Is it safe to assume that Arrow Lake were done as monolithic on N3B it could potentially clock higher because of the lower power floor, or would another variable offset that Fmax?
A bit OT- Are there any good sources for transistor count of Arrow Lake? There are some opportunities for logic reduction, as ARL lacks SMT on the P-Cores. In addition, ARL has more cache than Raptor Lake (+50% L2, addition of "L0" cache) in theory reducing per transistor power density. The E-cores are definitely significantly more transistor heavy though.
(Last note - I think the +100 MHz 8-core Zen 3 refresh chips *could* be TSMC rounding the corners, but I think it's more likely AMD is releasing something annually to keep OEMs happy as they always prefer "new" products. The 5900XT being a 5950X with 100 less MHz, and the fact that the 5700X3D actually came out *after* the 5800X3D seem to be good examples of this. 5700X3D also helps maintain the 'mindshare' price of an x800 level part).
Old IEDM/VLSI papers can be found on IEEE and go through many of the characteristics that process engineers will pour over (Ion, Ioff, DIBL, SS, etc). The closest you can get to an "all encompassing" performance number for a node would be ring oscillator frequency. It doesn't give you the whole picture and it isn't 1:1 with product Fmax for a whole host of reasons, but it is a common like for like comparison between process technologies (sort of like how people will run ARM testchips to compare PPA between nodes).
If you don't have an IEEE subscription to look through here are some freely available round ups of IEEE/VLSI coverages with common charts that get disclosed included:
Process Technology at IEDM 2008
David Kanter discusses 32nm process technologies presented at IEDM 2008 and VLSI 2009, including a discussion of high-k dielectrics and metal gates, immersion lithography and double patterning. Results from key manufacturers such as Intel, IBM/AMD, TSMC, Toshiba and others are discussed...
www.realworldtech.com
Intel Delivers Leading-Edge Foundry Node with Intel 3 Technology; on Path Back to Process Leadership
Editor’s Note: Welcome to the new Intel Foundry blog! We're launching this resource as a new way to peek inside our systems foundry for the AI era with some of the experts making it happen. We're thrilled to launch the blog with this exciting look at the Intel 3 node’s performance gains from...
community.intel.com
But there are some other important criteria that aren't always disclosed like switching energy, SRAM Vmin, and some things that are process-design co-dependent like which devices are using which VTs and capacitance. Good example is early N5 vs more mature N5. On early N5 there are dummy metal lines to make patterning easier, and on newer N5 chips you can see the dummy metal no longer being present to provide a capacitance reduction once TSMC got ahold of their M0 process.
I would lean towards not appreciably. I would guess that N3B being a less mature process than intel 7 (2 years in HVM vs 5 years), and more significantly the Cdyn/leakage components of power are more of a determent. But I am really not any kind of authority on that. I lean towards assuming the Cdyn is the bigger deal due to Zen5 going from whatever vintage of N5P-HPC they used to whatever vintage they went with on N4P-HPC and still having a significant turbo speed regression (especially in all core work loads).
Not that I know of.
I don't understand what you mean, more SRAM would increase both the active and leakage power. As for the logic side, intel claims axing SMT reduced the P core's Cdyn by 20%. But they also added all of that cache, and significantly widened many parts of the core. So I would assume P core Cdyn is much higher gen on gen in addition to having more leakage (at the very least more leakage@iso process).
Not worded great by me. So yes those parts likely exist for the reasons you said. What I meant is that by rounding out the corners the percentage of AMD's dies that can hit a given freq at some voltage and power spec increases. Allowing AMD to make a slightly better part, at same power, and cost. Also without having to certify a new process revision because those two products presumably use the same exact process but cleaned up. But I don't know 100% for sure that is how those parts are possible, just deductive reasoning of this being the lowest effort way for AMD to provide a slightly different product to better service the market.
That is my bad. I forgot the 5700X3D came out after not before the 5800X3D.
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Back at 28nm there was the Common Platform Consortium where IBM, Samsung, Chartered Semi and Globalfoundries teamed up to compete against TSMC. While it provided hope of a true TSMC competitor it failed. The process recipe did not yield and was not compatible with TSMC. UMC went on to make a T like compatible 28nm and did quite well. Samsung and GF did custom 28nm versions that was also a success but nothing compared to what TSMC did. That was a big NOT TSMC node. Samsung 14nm was also a good NOT TSMC node and Samsung even got some of the Apple iPhone business (iPhone 6+). 7nm was also good for Samsung but they tanked at 10nm and below and now seem lost (Samsung IDONTKNOW 2.0).
My suggestion is that Intel do a Common Platform type of deal offering leading edge process technology partnerships through Intel fabs to other foundries. Kind of like what Intel is doing with Tower and UMC at mature nodes but on a much larger scale with an ecosystem and all of the trimmings. These foundries would get First Class treatment like the top TSMC customers who are exclusive to TSMC.
GF and UMC are now boutique foundries with market niches that they could expand without the expense of building fabs and the associated R&D. They would just need to customize the Intel process for their niches. Samsung could do the same for their internal products and even offer foundry services for external customers and create their own boutique niches by bundling in their memories and other IP.
Sound reasonable? Put Intel back in a leadership role and make USA Semiconductor Great Again?
My suggestion is that Intel do a Common Platform type of deal offering leading edge process technology partnerships through Intel fabs to other foundries. Kind of like what Intel is doing with Tower and UMC at mature nodes but on a much larger scale with an ecosystem and all of the trimmings. These foundries would get First Class treatment like the top TSMC customers who are exclusive to TSMC.
GF and UMC are now boutique foundries with market niches that they could expand without the expense of building fabs and the associated R&D. They would just need to customize the Intel process for their niches. Samsung could do the same for their internal products and even offer foundry services for external customers and create their own boutique niches by bundling in their memories and other IP.
Sound reasonable? Put Intel back in a leadership role and make USA Semiconductor Great Again?
fansink
Well-known member
After deeper and deeper losses (and ~deeper yet after 3Q24 earnings in a few days), emergency BOD meetings, former BOD calling for breakup, growing buyout rumors, foundry alliance meetings with Samsung...
This is not the aura of a successful company, or a company on the mend.
It is a blinking sign a company needs to pivot. Hopefully Pat G sees this now. Let's see what the next investor call yields. Intel has missed so many semiconductor megatrends with AI being the latest one. It's the whole hockey analogy "Skate to where the puck is going not where it has been".
There's no point to develop the process if intel isn't getting paid a lion's ransom in royalties for all of their upfront investment. If the licencing fees are that high, then I suspect others have no incentive to build EUV capable fabs because the payback period is way too far in the future to justify the risk over just doing what is known to work. Nor do GF or UMC have the cash flows to just pop down 5-6 years of revenue just to build out the capacity needed support intel internal volume commitments). As an example let's say we talk foundry standard margins of 40%. Let's say intel needs a bit more than half the profits (25%) to justify the R&D, their capex in Oregon, as well as a cut for the fact that nobody else in the alliance could develop leadership process technologies at high yield. Okay that leaves 15% for partner foundries. I doubt UMC/GF would be eager to slap down like $50B for whatever their equivalent of 3-4 TSMC style fabs of 14A is, while also needing to build an ecosystem and provide their own IPs for a measly 15% GM. I also don't really know how one would develop a process while outsourcing the base IP, standard libraries, and PDK to multiple other foundries. Seems like a recipe for having execution slips or at best a sub-optimal DTCO solution for designers. IBM could get away with the licensing model because semiconductors were just the price of admission for IBM to make their mainframe products. For intel foundry, GF, UMC, and Samsung the wafers are not a cost center but the value is created/how they get paid.
Not technically feasible. The only old intel processes still in HVM are i14nm and i7. Both technologies would IMO take so much effort to rework the processes, develop new IPs/standard cells/design tools/design collatorals into something suitable for external use that you might as well just design a new process. That is also before you even add all of the development for the specialty features people would expect from a legacy node. The cost of doing that would seem too prohibitive when wafer ASPs would be low for a trailing edge process. I also doubt there is any demand for a brand new 10nm class or 7nm class logic process technology even if you did put in all of that effort. Also I don't think that solves intel's problem of needing to buy more time for cost effective process technologies to ramp internally and then gradually build external revenue. If anything outsourcing their production sounds like a great way to make it even worse...
The only cost effective use I can think of for intel's non EUV process technologies is running in their pre-EUV fabs making internal products while slowly switching over to running other foundry's process technologies as internal volumes for those processes dry up (ala Tower 65nm in Fab 11x or the co-developed 12nm with UMC in Fabs 12/22/32). Since F24 will be busy with i16 and can concievably put some overflow non EUV intel 4/3 tooling if they don't need all of F24 for i16, the only fab that needs to be filled at this point is F18/28 in Israel as intel 7 gradually winds down. Not as good as intel capturing 100% of the value, but better than sitting idle, and at least those fabs have already paid for themselves.
I would just continue to do what I can to buy more time and milk the maximum value from products with minimal investment to just sustain the current money making product lines until foundry achieves "escape velocity" in 2027. From there you can start phase two of fully transitioning intel back to a fab first company with eyes set towards external revenue exceeding Samsung internal+external in 2030 with UMC like margins. Option two if you still have faith that DCAI and NEX can turn into major growth stories (making it so CCG isn't the only money making venture inside of products and a stagnate one at that), then I think you pull in external funding and try to get other firms to become investors in IF (as retail investors have already spoken that they value IF less than the value of firesaleing its assets). I picture something similar to how SK is a large shareholder in Kioxia, or if you want to get crazy with it something IM-Flash like but where intel is the 51% rather than the 49%. That way you can at least still benefit from margin stacking.