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I totally expected this Arrow Lake debacle. TSMC's processes are less optimized for high speed transistors than Intel's.
The initial process clients at TSMC are typically smartphone chips, their processes are focused on low power.
Intel also disabled SMT. Reducing the peak multi-threaded performance of the processor.
So it cannot win in single-threaded performance because of the slower transistors, and it cannot win in multi-threaded because they cut SMT.
Consider that Intel has achieved this kind of piddling performance on a more advanced TSMC process (N3B) than what AMD is using in Zen 5 (N4X). And then you will realize just how lackluster their processor design is.
Arrow Lake cannot win against Zen 5 even with a process advantage. It cannot win with a memory speed advantage, and more expensive motherboards.
I totally expected this Arrow Lake debacle. TSMC's processes are less optimized for high speed transistors than Intel's.
The initial process clients at TSMC are typically smartphone chips, their processes are focused on low power.
Intel also disabled SMT. Reducing the peak multi-threaded performance of the processor.
So it cannot win in single-threaded performance because of the slower transistors, and it cannot win in multi-threaded because they cut SMT.
Consider that Intel has achieved this kind of piddling performance on a more advanced TSMC process (N3B) than what AMD is using in Zen 5 (N4X). And then you will realize just how lackluster their processor design is.
Arrow Lake cannot win against Zen 5 even with a process advantage. It cannot win with a memory speed advantage, and more expensive motherboards.
My guess is Intel would have to design a processor more suitable to the TSMC process.
A wider processor since they cannot push the clockspeed as high as on their own internal processes.
This should all be moot come next year after Panther Lake comes out in 18A though. Fingers crossed.
I do think Intel needs something to replace their longstanding P and E core families. And Royal Core could have been it. They would have also cut their core design teams in half, just like AMD which can handle everything from laptop to server more or less with a single core design.
The P and E core designs were a solution to the issue of being behind in terms of process. To keep the performance level while remaining at an appropriate die size despite being behind in terms of transistor density. But right now I think they should go for a different kind of processor architecture.
Intel could have tried to do something similar to the smartphone SoC vendors. Have one core out of the processor run at higher clockspeed, or be wider, to win at single-threaded benchmarks.
It still sucks that because they disabled SMT they went from a 32 thread processor with Raptor Lake to a 24 thread processor with Arrow Lake despite the same number of 8-P and 16-E cores. A regression. Compare that with Zen 5 with 32 threads on 16 large cores. Sure the P and E cores are wider on Arrow Lake but that won't matter in some thread heavy and work light workloads.
But I think the biggest mess is the lack of polish in this launch. They need to fix those OS/firmware issues ASAP.
I totally expected this Arrow Lake debacle. TSMC's processes are less optimized for high speed transistors than Intel's.
The initial process clients at TSMC are typically smartphone chips, their processes are focused on low power.
Intel also disabled SMT. Reducing the peak multi-threaded performance of the processor.
So it cannot win in single-threaded performance because of the slower transistors, and it cannot win in multi-threaded because they cut SMT.
Consider that Intel has achieved this kind of piddling performance on a more advanced TSMC process (N3B) than what AMD is using in Zen 5 (N4X). And then you will realize just how lackluster their processor design is.
Arrow Lake cannot win against Zen 5 even with a process advantage. It cannot win with a memory speed advantage, and more expensive motherboards.
Yeah about that it is not the process but the interconnect fabric and slower L3 which is hurting it the cores are starving from initial benchmarks from people
Yeah about that it is not the process but the interconnect fabric and slower L3 which is hurting it the cores are starving from initial benchmarks from people
Intel has been known for traditionally being better at SRAM cell design than their competitors. Going to a TSMC process they probably are using the foundry cell libraries so that advantage also goes out of the window.
The interconnect fabric does not explain having lower P-core clockspeeds than Raptor Lake. It is all about the transistors.
AMD has much worse fabric interconnect performance than Intel. So what is their excuse for having worse performance?
Apparently TSMC Process are not suitable for what Intel has their Process for High Clocks TSMC Process are good at low power but falls off at higher voltages way to quickly from the looks of it
Here is a reference of 285K with different clock multiplier fyi x =100 mhz and the multiplier is the internal CPU Multiplier it takes extra point 0.2V for extra 200Mhz
Apparently TSMC Process are not suitable for what Intel has their Process for High Clocks TSMC Process are good at low power but falls off at higher voltages way to quickly from the looks of it
Here is a reference of 285K with different clock multiplier fyi x =100 mhz and the multiplier is the internal CPU Multiplier it takes extra point 0.2V for extra 200Mhz View attachment 2390
I hate to break it to you, but EVERY processes technology since the dawn of man has a V-f curve that falls off a cliff at high voltage. This isn't a TSMC exclusive phonemina look at any chip ever made. You will see the same thing. See the last page for why ARL actually has a lower Fmax.
Spoiler alert: Intel 7 is not higher performance than Intel 4 or N3...
