If you are ready to share your expertise with the chip, board & systems design community, then it’s time to submit your proposals for the DesignCon 2014 Technical Program. The conference will be held January 28-31, 2014 at the Santa Clara Convention Center in Santa Clara, CA.
The conference welcomes proposals for technical papers, panels and tutorials. Wondering what’s the difference? Technical papers are up to 25 pages long, address design case studies and application overviews, and are presented in forty-minute sessions. Technical panels are 75-minute presentation/discussion sessions featuring 3-5 panelists plus a panel chair to moderate the discussion.
Tutorials are half-day (three-hour) sessions with papers up to 50 pages long, allowing the speakers to cover their topics in greater depth and breadth. (Tutorials are scheduled for Tuesday, January 28; the technical paper sessions will be held on Wednesday–Friday, January 29-31; technical panels are scheduled on Tuesday-Thursday at the end of each day's program.)
Topic Categories (You can see sample topics for each track here.)
Past speakers have included:
Analog engineers, application engineers, CTOs, design engineers, directors of engineering, editors, EMC engineers, engineering managers, Fellows, hardware engineers, members of technical staff, principal engineers, product engineers, professors, R&D engineers, signal integrity engineers, systems engineers, technical directors, VPs of engineering and more.
How to Submit Your Proposal
View instructions on what information is needed to submit
Read our review criteria on how submissions will be selected
When you're ready: submit your proposal online here
Deadline to submit: Friday, July 26, 2013
Final drafts of papers selected for the program will be due by November 19, 2013.
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The conference welcomes proposals for technical papers, panels and tutorials. Wondering what’s the difference? Technical papers are up to 25 pages long, address design case studies and application overviews, and are presented in forty-minute sessions. Technical panels are 75-minute presentation/discussion sessions featuring 3-5 panelists plus a panel chair to moderate the discussion.
Tutorials are half-day (three-hour) sessions with papers up to 50 pages long, allowing the speakers to cover their topics in greater depth and breadth. (Tutorials are scheduled for Tuesday, January 28; the technical paper sessions will be held on Wednesday–Friday, January 29-31; technical panels are scheduled on Tuesday-Thursday at the end of each day's program.)
Deadline to Submit proposal: Friday, July 26, 2013. Papers due: November 19, 2013.
Submit a proposal here.
Submit a proposal here.
Topic Categories (You can see sample topics for each track here.)
- Optimize Chip-Level Designs for Signal and Power Integrity: Chip-level decisions can make or break the high-performance interface. This track covers a wide variety of signal and power integrity topics at the on-chip level, from interconnect topologies, transceiver technology and design, to noise and jitter mitigation strategies.
- Overcome Analog and Mixed-Signal Design and Verification Challenges: Today’s chips possess an abundance of analog, mixed-signal, and RF functionality necessary for intra-system and real-world interfacing. This track addresses challenges and solutions encountered in the design, verification, and system modeling of AMS & RF technology from a perspective beneficial to both chip and system design engineers.
- Wireless and Photonic Design & Integration: The aim of this track is to provide a forum covering practices and methodologies used in emerging system designs and applications leveraging wireless and photonic technologies as media for data transmission.
- Optimize System Co-Design: Chip/Package/Board: This track covers a broad range of topics addressing design-oriented modeling simulation and analysis for cost-effective power and signal integrity performance optimization of Chip/Package/Board/Chip+Package+Board for modern microprocessor/digital systems.
- Characterize PCB Materials and Processing Characterization: Printed circuit boards (PCBs) can no longer be viewed as passive platforms for mounting and interconnecting electronic components. This track considers how PCB materials and fabrication processes can affect the electrical properties and performance of the circuitry mounted on the board.
- Apply PCB Design Tools and Methodologies: High-speed data transfer and telecommunications are supported by PCB platforms that typically constitute over 80% of the channel length while concurrently supporting power delivery, mixed-signal requirements and full-blown serial data speeds. This track explores effective high-speed design and design choices using a wide range of E-M modeling techniques, PCB characterization tools and test platforms to optimize PCB platforms such as backplanes, mid-planes and daughter cards combined with separable interconnects and optical channels.
- Design Parallel and Memory Interfaces: Memory and parallel interface designs continue to be challenged with complex performance requirements including bandwidth, power consumptions, and form factors. This track addresses the latest design techniques and signal and power integrity issues to meet these performance requirements for various chip-to-chip interfaces. I/O system used in 2.5D, 3D, on-chip, SiP, and MCM are covered in this track in addition to conventional on-board interface designs.
- Optimize High-Speed Serial Design: Systems designers must resolve a complex set of tradeoffs among package/board/backplane design, choice of connector/materials, SerDes transmit/receive equalization capabilities, and signal coding schemes to get the high speed serial channels in their system to meet both performance and cost requirements. This track presents system analysis techniques, design studies, and technology/performance data to help system designers make design and technology choices that are as effective as possible.
- Detect and Mitigate Jitter, Crosstalk, and Noise: The only relevant signal integrity issue is whether or not a system operates at the required bit error ratio (BER). This track concentrates on the causes of errors, including, but not limited to jitter, crosstalk, and noise, and techniques for measuring and estimating BER performance such as total jitter and BER contour.
- Leverage High-Speed Signal Processing for Equalization and Coding: High-speed communication systems require increasingly complex signal processing techniques, including equalization, modulation, timing, detection and forward error-correction methods. This track covers design, modeling, analysis and implementation of such techniques.
- Ensure Power Integrity in Power Distribution Networks: Power Integrity, distribution and management are essential for system functionality and performance. This track addresses power regulation; power distribution network design, modeling and analysis on boards, packages, and silicon; and it emphasizes the modeling and analysis of supply noise and its impact on overall system performance.
- Achieve Electromagnetic Compatibility and Mitigate Interference: The electromagnetic compatibility (EMC) and interference (EMI) track aims to cover topics related to the electrical modeling, simulation, and validation for product compliance and certification due to EMI/EMC issues. This track raises the awareness and the impact for design and systems engineers in order to mitigate possible issues in the early design stage.
- Apply Test and Measurement Methodology: This track focuses on advancements in measurement techniques for all aspects of signal and power integrity with an emphasis on understanding the practical limitations and quality of the measurement as well as the accuracies involved when trying to match simulations with measurements.
- Ensure Signal Integrity with RF/Microwave/EM Analysis Techniques: Analysis of signals on interconnects with high data rates is evolving to include the extension of techniques originally developed for digital and RF/microwave systems. This track covers signal integrity analysis techniques for interconnects and passive components of digital and RF/microwave systems as well as the analysis validation with measurements.
Past speakers have included:
Analog engineers, application engineers, CTOs, design engineers, directors of engineering, editors, EMC engineers, engineering managers, Fellows, hardware engineers, members of technical staff, principal engineers, product engineers, professors, R&D engineers, signal integrity engineers, systems engineers, technical directors, VPs of engineering and more.
How to Submit Your Proposal
View instructions on what information is needed to submit
Read our review criteria on how submissions will be selected
When you're ready: submit your proposal online here
Deadline to submit: Friday, July 26, 2013
Final drafts of papers selected for the program will be due by November 19, 2013.
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