Chipworks confirms pretty much all of the Intel 14nm process minimum features size

[astilo]

Intel?s 14-nm Parts are Finally Here! | Chipworks Blog

So, the chip has a THIRTEEN layers of metal, and a MIM-cap layer under the top metal (Intel has been using nine for the last few generations, going up to eleven in the Baytrail SoC chip).
The contacted gate pitch looks pretty close to 70 nm and the Fin has a 42-nm pitch. Only the Intel quoted 52 nm interconnect pitch, is a bit larger at 54nm (although that is within measurement error, and they may not have sectioned the most tightly packed part of the die).
SRAM cell size in the cache memory is ~0.058 µm2 as per Intel slide.

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[IanD]

Intel?s 14-nm Parts are Finally Here! | Chipworks Blog

So, the chip has a THIRTEEN layers of metal, and a MIM-cap layer under the top metal (Intel has been using nine for the last few generations, going up to eleven in the Baytrail SoC chip).
The contacted gate pitch looks pretty close to 70 nm and the Fin has a 42-nm pitch. Only the Intel quoted 52 nm interconnect pitch, is a bit larger at 54nm (although that is within measurement error, and they may not have sectioned the most tightly packed part of the die).
SRAM cell size in the cache memory is ~0.058 µm2 as per Intel slide.

There's no doubt Intel's pitches and RAM cell size are smaller than anyone else's "14nm/16nm" process. But Intel are using SADP to make CPUs, the design rules are much more restrictive and the design time/effort is much larger and more expensive, but this (and 13-layer metal) is OK if you're making a few high-margin CPU designs with massive revenue and profit per design since you can afford a thousand man-years or so per chip (I work with some ex-Intel guys). In contrast, all the foundries are using LELE (double-patterned "20nm" metal stack) to make SoC, where such restrictive design rules and design time/costs are not acceptable because the gross margins are much smaller.

So Intel's process does appear more advanced, but only because the application it's used for allows it to be and can pay for it -- which is great for Intel. But there's no way Intel can use this process to make SoC which compete with TSMC, GF and Samsung, the cost would be too high -- not just wafers but also design and mask costs. To compete in the SoC market they'd have to do a process optimised for SoC which would end up looking very similar to the foundry processes, except probably more expensive and with lower margins than Intel are used to, and they'd need much better process and IP support than at present -- and this would only make sense if it didn't take capacity away from their CPU lines.

It's an Apple process (small range of high-priced luxury goods, big volume and even bigger profits each) not a Samsung one (huge range of goods covering all markets, bigger overall volume but smaller profits).

 

[khaki]

Actually in that figure, the quoted metal pitch of 54nm only appears in a tiny portion of the cross-section at M4. If you average out over the whole cross-section, M4 has an average pitch of about 65nm, close to what foundry is using, and M2 has an average pitch of about 75nm. Of course, this is just a single cross-section and other parts of the chips might have a denser metal. Maybe in GPU?

On the other hand use of SADP as opposed to foundry's LELE, restricts the design. One could imaging a bidirectional M1 being roughly equivalent of M1+M2 for local routing. Wrong-way metals are doable with SADP, but at much relaxed pitch. The cross-section that shows the entire metal stack suggests >210nm for wrong-way metal pitch, but again that's just a single cross-section.

 

[Daniel Nenni]

Great analysis thus far, thanks.

FYI: I spoke with Sunit Riki (Intel Foundry VP) about the foundry side of things at Intel. He assured me that the Intel Custom Foundry processes are not the same as the ones used for microprocessors. Here are his slides from SEMICON:

http://www.semiwiki.com/forum/files/2Sunit Rikhi_Intel.pdf

Intel offers two versions of 14nm for foundry customers, general purpose and low power (slide #12). I asked directly if the low power one is what Intel uses for their SoCs and if I remember correctly the answer was yes. My guess is that Altera will start with the general purpose one. Hopefully Intel will have a 14nm SoC available for tear down soon so we can see what is inside. I'm looking forward to the Altera 14nm tear down as well to see how it compares to the Xilinx 16nm part. Silicon doesn't lie.......

I truly feel that holding the semiconductor industry accountable for misleading competitive data is for the greater good. With third party tear downs, public benchmarks, and social media, transparency is now an important part of corporate marketing communications, my opinion.

 

[IanD]

So are the Intel Foundry processes the same as the CPU one (fine pitch using SADP) or more like other foundries (LELE with bigger pitch)?

 

[astilo]

I would suggest Intel to remove this sentence from their marketing slides for the foundry business:

Intel has ~3.5 year lead in introducing revolutionary transistor technologies

It was partially true (do not get me wrong), but it also means that they are literally loosing ground (best guess they have 1 year lead at 14nm and 0 year or even negative for the SoCs release) and moreover, even with this huge time advantage, they haven't succeed in the past.
As a potential customer, my question after seeing that statement would simply be: so, why are you not yet a foundry leader?