Chip development flow

[sharanbr]

Hello All,

I am interested in getting some details on chip development. I am involved in front end development work.

I do understand the front end to a large extent. What I am interested is beyond tapeout.
I am especially interested in tasks that are not generally listed exclusively or are very niche.
For example, post-silicon validation is obvious but wafer sorting, package design, reliability testing, assembly etc. is not clear.

I would like to get all these steps listed. All I am looking for is just steps not in-depth description of these ...

 

[Daniel Payne]

Sharanbr,

Here are some post-tapeout steps:

• Mask making
• Wafer-level testing
• Die are separated from the wafer
• Good die are packaged, bad die are recycled
• For 2.5D and 3D chips the multiple, known good die are assembled
• Packaged die are tested
• Some packaged die are binned according to speed (i.e. - Slow, Medium, Fast)
• Buyers receive packaged die, some do incoming testing
• Packaged chips are mounted on a PCB
• PCB is tested

Does that help?

 

[sharanbr]

Dear Daniel,

Thank you. It does help.

I have several follow-up questions ...

• Wafer-level testing

I assume wafer level testing is done mainly to isolate manufacturing defects. Is this correct?

If the volume of chips is less (sample/proto chips) then does it make sense to do wafer testing?
Instead, skip this and go for testing of packaged chips.

• Good die are packaged, bad die are recycled
• For 2.5D and 3D chips the multiple, known good die are assembled

I am new to packaging concepts. Even in case of monolithic chips, wouldn't there be assembly.
You have written assembly only in case of 2.5D & 3D. Hence my question.

• Packaged die are tested

Assuming testing was done at wafer level and above testing means ATE level testing, what level of testing is carried out
at this stage? Would it repeat what was done at wafer level. My understanding is that we have got known good die and hence
there is no need to repeat tests that are needed for die. All we need at this stage is testing to rule out any issue related to
packaging.

• Some packaged die are binned according to speed (i.e. - Slow, Medium, Fast)

What is the use of this segregation? The end users, to my knowledge, never get to know the timing corner
that a specific chip lies in.

Some additional questions below please,

• what is meant by wafer sorting (heard this term many times and have done lot of online search. Its not clear to me)
• What exactly is meant by KGD? Does it mean that it is free from manufacturing faults.

I believe this category exists at die level and hence I am assuming that functional testing, if any, is very limited

• is it normal for package house to package design also?
• Apart from ATE level testing to isolate manufacturing defects, what other tests are done by semiconductor device manufacturers (both IDM and Fabless). I am aware of functional testing, electrical testing etc. I keep hearing lot of other tests on silicon like margin testing etc. I would like

to know more. Also, are there any reliability testing etc. that are carried out by device manufacturers?

• From a testing perspective, one thing that confuses me a lot is what type of test is applied to every single chip and what type of test is

applied to only to a certain samples and what type of test is done just once ...
For example, I would assume device characterization is not done on all the chips. I would like to know more ...

 

[Daniel Payne]

Yes, wafer-level testing is the first electrical test of the new IC and it's looking for good and bad chips. A bad chip can have either a defect so that it fails, or have timing that is outside of specification. The package can cost more than the die, so it makes sense to test the die before committing to a package.

Assembly can mean that the die is placed inside of a package, and then wires attached to the bonds on the die.

A packaged die may have a new failure, so you need to be 100% certain that all is still well. Also a packaged die may have thermal issues, so testing is paramount. A packaged test is typically more thorough than a wafer-level test.

For memory, CPU or GPU devices the supplier will sell different speed classes. They are all designed be the highest speed, yet due to manufacturing imperfections some of the chips will be slower than others, hence binned to a different speed category. Slower parts also have a lower sales price.

Wafer sorting is the process of testing a die while it's still on the wafer, then "sorting out" what is a good or bad die.

KGD - Known Good Die means that the die passed tests at the wafer level, and is ready for packaging, assembly or direct sale without being packaged. The level of testing depends on what the buyer wants tested.

Package service companies typically offer both package design and test services.

Inputs to an IC have a timing specification called setup and hold time. The amount that they pass the specification is called "margin".

There is ESD - Electro Static Discharge testing, IDDQ (quiescent current) testing, scan testing, Idd current testing, voltage level input testing. There can be testing for alpha particles, Single Event Upset, soft error rate testing, peak current testing, slew rate testing, Vdd voltage testing, pattern sensitivity testing.

Testing depends on the type of design: Digital, Analog, AMS, Memory, CPU, GPU, etc.

There are test engineers (aka product engineers) that spend their lifetime in this area, so it is a very broad topic. The premier test conference is called ITC, International Test Conference

Device characterization is done by the fab or foundry during process development, and it helps them build the Process Design Kit (PDK) for use by EDA tools.

 

[sharanbr]

For memory, CPU or GPU devices the supplier will sell different speed classes. They are all designed be the highest speed, yet due to manufacturing imperfections some of the chips will be slower than others, hence binned to a different speed category. Slower parts also have a lower sales price.

Thank you. I did not think about this.

There is ESD - Electro Static Discharge testing, IDDQ (quiescent current) testing, scan testing, Idd current testing, voltage level input testing. There can be testing for alpha particles, Single Event Upset, soft error rate testing, peak current testing, slew rate testing, Vdd voltage testing, pattern sensitivity testing.

to the best of my knowledge, all this can be handled at ATE level. Couple of questions here,

• would this testing be applied for every shipping chip?
• when tests are done for advanced protocols like PCIe where eye diagrams are captured & analyzed. Would those tests be done for every chip?

There are test engineers (aka product engineers) that spend their lifetime in this area, so it is a very broad topic. The premier test conference is called ITC, International Test Conference

Thank you. I will take a look.

Device characterization is done by the fab or foundry during process development, and it helps them build the Process Design Kit (PDK) for use by EDA tools.

Ok. So, when a foundry embarks on a new technology node, it first builds chips which are then used to characterize various process & device parameters.
Am I correct?

 

[Daniel Payne]

sharanbr,

From the list of types of tests it depends on what the foundry is looking for, as to whether or not all chips are tested that thoroughly. For reliability tests like Single Event Upset, and Soft error rate they typically just use a handful of chips as a quality control sample.

Yes, the foundries design and build early test chips for each new process generation and then run exhaustive characterization on them in order to create the PDKs. In addition to actual fabrication, they can also simulate a process and predict device parameters without having to actually fabricate anything.

 

[sharanbr]

Dear Daniel,

Thank you very much ...

 

[barun]

If the volume of chips is less (sample/proto chips) then does it make sense to do wafer testing?
Instead, skip this and go for testing of packaged chips.

Partially correct. Yes if the volume of chip is less one does not do wafer level testing. But in production also sometimes one can avoid wafer level testing, particularly when the package cost is a significantly small portion of total ASIC manufacturing cost (die cost + package cost + test cost) and the package yield is very high. It all depends on the how much extra cost ones is incurring in the wafer level testing and how much ones is loosing by allowing bad die to get packaged

What exactly is meant by KGD? Does it mean that it is free from manufacturing faults

KGD is predominantly used by memory vendors who sell bare memory dies to other SoC companies who assembled those bare die with their own bare die (typically a processor) in a 2.5D/ 3D package

 

[barun]

Would this testing be applied for every shipping chip?

• when tests are done for advanced protocols like PCIe where eye diagrams are captured & analyzed. Would those tests be done for every chip?

Functional testing are done only a portion of chip. This test needs significant hour to run and hence running at every chip is economically unviable. Also it is very unlikely that some chips in same lot will fail functional testing and some will pass it all those passed electrical testing

 

[sharanbr]

Partially correct. Yes if the volume of chip is less one does not do wafer level testing. But in production also sometimes one can avoid wafer level testing, particularly when the package cost is a significantly small portion of total ASIC manufacturing cost (die cost + package cost + test cost) and the package yield is very high. It all depends on the how much extra cost ones is incurring in the wafer level testing and how much ones is loosing by allowing bad die to get packaged

Do wafer handlers/probes cost a lot of money. Because this is one tool that is needed if one were to do wafer testing.

KGD is predominantly used by memory vendors who sell bare memory dies to other SoC companies who assembled those bare die with their own bare die (typically a processor) in a 2.5D/ 3D package

I would assume that KGD can be used almost for any type of chip and it probably signifies if vendor who is supplying the die is delivering with or without testing. My opinion. I could be wrong though.

 

[sharanbr]

Functional testing are done only a portion of chip. This test needs significant hour to run and hence running at every chip does not make sense.

I would like you to re-think when you say "does not make sense". Just because something takes time does not mean that it does not make sense. It may make things unwieldy & hard though.

Also it is very unlikely that some chips in same lot will fail functional testing and some will pass it all those passed electrical testing

I guess what a semiconductor vendor guarantees is a certain % of testing of chips that land up at its customer's hands.
So, if a test is done to guarantee X% testing then those have to be done on every chip I guess.

I do agree with you that that it is unlikely that one chip from same wafer has passed functional test and other does not.
But this is the case with other structural tests like ATPG also.