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[I commented on that, but since it's Cadence's own site it may not appear.]
"Fast Spice" should have been replaced by Verilog-AMS where you can use behavioral models and tune the precision, unfortunately Cadence stymied that by blocking the only back-annotation proposal and never producing a promised alternative, so mixing behavioral models and extracted wiring is not a supported flow. Since nobody at Cadence has brought up fixing the problem at the Verilog-AMS committees I'll assume if they have something "new" in mind that won't be it.
Spice itself is a bad level to simulate at because the transistor models are intrinsically unstable mathematically - which is why convergence is often a problem. However, very few circuits use transistors singly, and it should be possible to do a mathematical reduction of groups of transistors to get stable models for components like gates, op-amps, amplifiers, PLLs etc. which are faster and equally accurate. Unfortunately, the transistor model definitions are done in a style (BSIM) that doesn't lend itself to that. There are less formal techniques which you can use to extract the appropriate equations, but I have not seen anyone do it yet.
The second bottleneck in Spice is the solver, but that is more crucial for the internal evaluation of models as mentioned above which can be eliminated by using composite behavioral models, so faster techniques can be used with behavioral models.
simguru,
Thanks for the insight. I'd love an EDA tool that would read my SPICE netlist and then automatically abstract a behavioral model for faster simulation. Write that EDA tool and I will market it, then we will get rich and retire.
Since Cadence having been pushing a "wreal" methodology and completely borked discrete analog modeling in SystemVerilog (with Mentor's help) I am not expecting anything radically new here. Most likely it's just a rewrite to take advantage of GP-GPU or multicore.
It's probably worth noting here that low-gain devices are easier to handle in simulation and lumping passive components can be handled analytically, so simulation should get easier as dimensions shrink other than handling the bigger number of devices.
One reason progress is slow in this area is the tools guys are usually math or computer science guys that don't actually understand circuits. Things would work better if folks who understand circuits could do the modeling - see Ian Getreu's thread on that.
simguru,
The only other EDA company to use a GPU for SPICE was Nascentric, and they went out of business. I recall they saw only about a 4X speed-up with a GPU compared to multi-core approach.
I interviewed with Nascentric - they said I didn't have enough "graph theory". I would say they went out of business because they didn't understand circuits, and tried to solve the wrong problem. If you want to use GP-GPU you need an approach that is mostly data-parallel, analog solvers tend not to be - so you need to know where more approximate methods work, which is circuit knowledge rather than mathematics. If you used Verilog-AMS (as above) the designers could annotate that information into the models, but working at transistor level in Spice that information is not available.
Unfortunately AFAIK for transistors you can only get calibrated and verified SPICE model data from a foundry. As long as that is the case (almost) no analog/mixed-signal project leader will expect anything other than a (fast-)SPICE simulator to verify a full-custom analog/mixed-signal block.
That's fair enough, but given that sub 45nm Silicon has fairly high variability, and extraction tools are only good to ~ 15%, I'm not sure what accuracy is actually required. You certainly want to align whatever simulator and modeling tools you have with the Spice data, but simulating at the single transistor level is not smart or necessary.
