[I commented on that, but since it's Cadence's own site it may not appear.]
"Fast Spice" should have been replaced by Verilog-AMS where you can use behavioral models and tune the precision, unfortunately Cadence stymied that by blocking the only back-annotation proposal and never producing a promised alternative, so mixing behavioral models and extracted wiring is not a supported flow. Since nobody at Cadence has brought up fixing the problem at the Verilog-AMS committees I'll assume if they have something "new" in mind that won't be it.
Spice itself is a bad level to simulate at because the transistor models are intrinsically unstable mathematically - which is why convergence is often a problem. However, very few circuits use transistors singly, and it should be possible to do a mathematical reduction of groups of transistors to get stable models for components like gates, op-amps, amplifiers, PLLs etc. which are faster and equally accurate. Unfortunately, the transistor model definitions are done in a style (BSIM) that doesn't lend itself to that. There are less formal techniques which you can use to extract the appropriate equations, but I have not seen anyone do it yet.
The second bottleneck in Spice is the solver, but that is more crucial for the internal evaluation of models as mentioned above which can be eliminated by using composite behavioral models, so faster techniques can be used with behavioral models.
