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LONDON — ZeroASIC has developed a technology platform to bring chiplets to embedded system design, as a time-efficient alternative to designing and manufacturing custom application-specific ICs (ASICs). The platform is based on swappable pre-fabbed 2 x 2 mm chiplets on an active silicon interposer, which customers can design for themselves in a matter of minutes using ZeroASIC’s online EDA tool.
The company’s aim is to reduce the barrier to making custom ASICs versus using off-the-shelf SoCs. ZeroASIC CEO Andreas Olofsson told EE Times that the biggest cost, in terms of both time and money, for custom ASICs is tapeouts.
“A tapeout might cost $10 million, and it takes 6 months to come out of the foundry,” he said. “So, if you want to make it faster, you clearly can’t have any tapeouts, and that’s where the chiplets come in.”
I was expecting to see a less educated person writing this one:
Sally Ward-Foxton covers AI for EETimes.com and EETimes Europe magazine. Sally has spent the last 18 years writing about the electronics industry from London. She has written for Electronic Design, ECN, Electronic Specifier: Design, Components in Electronics, and many more news publications. She holds a Masters' degree in Electrical and Electronic Engineering from the University of Cambridge.
“ZeroASIC will be a fabless semiconductor company selling packaged devices made up of its chiplets in different combinations. Prior to 2020, the company was known as Adapteva and had been working on parallel processors since 2008. Olofsson left to run DARPA’s CHIPS (Common Heterogeneous Integration and IP Reuse Strategies) program for three years before rejoining in 2020 to refocus the company as ZeroASIC. Today, ZeroASIC is entirely funded by revenue from existing U.S. government contracts and employs 18 people in the U.S. and Europe.”
“A tapeout might cost $10 million, and it takes 6 months to come out of the foundry,” he said. “So, if you want to make it faster, you clearly can’t have any tapeouts, and that’s where the chiplets come in.”
Similar argument to hardened FPGAs, remember when you could get an ASIC equivalent to an FPGA but you programmed in the fixed functionality by the top mask or two? Same idea of inventory just weeks away from ready, more efficient and compact than FPGA, simple EDA tools with easy simulation, no problems of physical verification. Whatever happened to that?
I think this approach is quite clever though the 2mm squares seem a little small, and I wonder where they will find the OSAT for that final bonding step in an industry scrambling for capacity to bond customers even with very large budgets to spend.
I think this approach is quite clever though the 2mm squares seem a little small, and I wonder where they will find the OSAT for that final bonding step in an industry scrambling for capacity to bond customers even with very large budgets to spend.
For interposers with bonded chips, press reports have said capacity is booked up to 2 years out and the ecosystem is investing heavily. It is a very technically challenging process.
I would expect that hybrid bonding a small swarm of 2mm chips onto a relatively modest base chip is quite different than bonding some GPUs and HBM onto a large interposer, but the capacity must be found somewhere, and I am not aware of any prior products that would have caused a similar OSAT capability to already exist.
