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I don't think TSMC would be using EUV with its stochastic issues. 5nm with larger pitches and double patterning with SALELE, even there, there is some risk, though less obvious than with direct print.
I mean that is mostly out of ASML's hands. They would need faster EFEMs, faster AMHS, faster and more precise deps/etches. Only thing they can do is improve throughput to slightly make it faster or lower EPE/LER for better CDs. Unless you mean speeding up low-NA tools and using low-NA triple or quad pattering vs high-NA SALELE?
Guess you are not familiar with stochastic effects. Some explanation for the terms you used here. CD is low frequency/long range feature width average. Typically we measure CD and report CD, Local CDU and Global CDU. LER is the line edge position variation from ideal line edge. It is vulnerable to SEM noises and distortion. EPE would be a little bit complex. you can refer to the explanation from ASML in the following graph which combines factors in two layers.
Imec doesn't expect any 3D stacking until like 2030-32. So while I think we will get to a NANDification of logic eventually. That doesn't sound to be happening until the mid 2030s at the earliest since TSMC has been pretty consistent that CFET then 2D then 1D for their 10+ year roadmap. As for high-NA I don't think it is about pushing to 8nm features (low-NA can't even do the 13nm). Fred, Tanj, and I were talking about this earlier. Since I don't want to put words in their mouths the TLDR of my thoughts was that the main application would be reducing multi patterning for middle layers rather than pushing min feature. For example doing something like N5's 30nm SALELE M0 with high-NA DP. If memory serves from a Nikon paper I read while ago they mentioned that DUV double patterning cost ranged from like 3-4x the cost of DP (depending on the scheme used) because you need at least 2x more litho, a bunch of extra non litho tools, and you drastically lower cycle time. Back to high-NA; if all you try to do is reduce the degree of multipatterning, now you only need the cost of a high-NA exposure to be to be like 2-3x the cost of low-NA exposure (adjusted the multiplier down because EUV is more expensive then DUV) for the fab to get a positive ROI.
I think it was like 2015 or 2016 was when the fist sudo HVM customer tools started being delivered. With the first sort of real HVM tools going to Samsung/TSMC in like 2017-2018 timeframe. Granted this is a smaller transistion then EUV so it seems we are skipping a lot of the growing pains of 2015-2018 since ASML claims like 200wph rather than the like 60wph for the 2015 tool.
Samsung 7LPP might have been first to double digit layers since they were fully EUV rather than just having it there as a side thing for yield learning like with N7+. Granted the throughput and or yield were so bad (my guess is mostly column A with some column B) that if memory serves it was practically vaporware until when N6/N5 were starting to rollout... Buuuut that's Samsung for you.
I mean that is mostly out of ASML's hands. They would need faster EFEMs, faster AMHS, faster and more precise deps/etches. Only thing they can do is improve throughput to slightly make it faster or lower EPE/LER for better CDs. Unless you mean speeding up low-NA tools and using low-NA triple or quad pattering vs high-NA SALELE?
Indeed the goal of the 3800 is to increase throughput, which would go with the EUV quad patterning and SALELE. Certainly TSMC would be getting more of these than the High NA in the near future.
Indeed the goal of the 3800 is to increase throughput, which would go with the EUV quad patterning and SALELE. Certainly TSMC would be getting more of these than the High NA in the near future.
Agreed. When trying to push resolution to the max, I don't think high-NA SALELE or SA-LE3 will be economical for like 12p metal lines or anything like that compared to low-NA SA-LE3 or SA-LE4. Maybe some day high-NA will be good beyond the features you can DP; but not today. Silver lining is we don't have to be too worried near term as logic and DRAM have other factors gating scaling to ultra fine pitches beyond lithographic resolution.
