Apple A17Pro transistor density

[nghanayem]

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N3E teardown is out. Nothing unexpected other than relaxing M1 pitch to have an intel 4/3 like pitch gearing. One thing that I never really connected the dots on, was their observation that N3E was more like an aggressively scaled N5 rather than a scaled back N3. With the full rearchetecting of N3E's FE, N5 -> N3E really does seem reminiscent of 10FF -> N7.

Speaking of, I don't really get why TSMC marketed N3E as a SRAM and logic density regression vs N3, it seems like they kind of shot themselves in the foot there.

 

[Maximus]

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N3E teardown is out. Nothing unexpected other than relaxing M1 pitch to have an intel 4/3 like pitch gearing. One thing that I never really connected the dots on, was their observation that N3E was more like an aggressively scaled N5 rather than a scaled back N3. With the full rearchetecting of N3E's FE, N5 -> N3E really does seem reminiscent of 10FF -> N7.

Speaking of, I don't really get why TSMC marketed N3E as a SRAM and logic density regression vs N3, it seems like they kind of shot themselves in the foot there.

tsmc usually let R&D to work on major nodes, like N7, N5, N3. Then fab work on sub nodes like N6, N4, N4P...
N3E is an unusual node that was also developed by R&D. So N3E and N3B can be seemed as developed separately.

N3E's advantages are better cost, yield and flexibility compared to N3B. I guess tsmc's major customers would not mind slight SRAM/logic density regression too much and make the slight regression statement is probably to prevent customers' expectation too high.

 

[Daniel Nenni]

tsmc usually let R&D to work on major nodes, like N7, N5, N3. Then fab work on sub nodes like N6, N4, N4P...
N3E is an unusual node that was also developed by R&D. So N3E and N3B can be seemed as developed separately.

N3E's advantages are better cost, yield and flexibility compared to N3B. I guess tsmc's major customers would not mind slight SRAM/logic density regression too much and make the slight regression statement is probably to prevent customers' expectation too high.

To be clear N3B was developed for Apple (mobile) so they pulled the strings on SRAM. Apple also has a set schedule.

 

[Fred Chen]

tsmc usually let R&D to work on major nodes, like N7, N5, N3. Then fab work on sub nodes like N6, N4, N4P...
N3E is an unusual node that was also developed by R&D. So N3E and N3B can be seemed as developed separately.

Independent R&D teams indeed.

 

[nghanayem]

tsmc usually let R&D to work on major nodes, like N7, N5, N3. Then fab work on sub nodes like N6, N4, N4P...
N3E is an unusual node that was also developed by R&D. So N3E and N3B can be seemed as developed separately.

That is why I wonder how much of a push the N3 delays had on A14. If TSMC only wants to have 2 R&D teams at fab 12, then A14 must have surely been pushed out somewhat (relative to their internal goals rather than their external commitments). Surely some people started transferring to the A14 program as N3 was getting transferred to fab 18's development/ramp team and N3E's time in fab 12 was finished up, but you would have still had a lot of folks spending an extra year or two on N3/N3E that could have been spent getting A14 out the door in 4 years rather than the 5-7 TSMC said for new node development going forward.

N3E's advantages are better cost, yield and flexibility compared to N3B. I guess tsmc's major customers would not mind slight SRAM/logic density regression too much and make the slight regression statement is probably to prevent customers' expectation too high.

To be clear N3B was developed for Apple (mobile) so they pulled the strings on SRAM. Apple also has a set schedule.

TSMC obviously deserves smoke on N3 being a year late and that product being an orphaned process to be replaced by a fullly rearchitected FEOL that is not DR compatible. As long as flubs like this stay an exception rather than delays and abandoned processes becoming commonplace like it was at 2000s TSMC, then customer trust in TSMC execution will remain.

With that less than savory preface out of the way, I think TSMC deserves a real good pat on the back for how well they handled the N3 situation. They had a fundamentally flawed process and from there you have a few choices such as brute force the issue, reign the process in to make it easier, rip it all up and start again. TSMC worked with their customers on the last point knowing that if they were going to run this process for a LONG time they wanted it to have a good cost structure and a low defect density floor. Doing this would have meant a very large delay especially if they weren't fast on starting this program. Therefore TSMC must have pretty early in the N3 development process realized they would need a redefinition, which really takes guts and a really good understanding of what you can and cannot do within a given time.

Of course this is all well and good for wave 2 and 3 guys. But what about their lead customer/product Apple A17 pro? In order to not be more than a year late TSMC continued to execute on their original N3 process to get it into a passable state. In another move that took guts and a strong understanding of their capabilities TSMC decided to do a couple percent optical bloat of the FEOL to ensure they could hit the intercept Apple needed. As well as working with Apple to make their lead product exist in a more limited subset of Apple's 2023 line-up.

In some ways the failures along the way to reach N3E do a better job showing how formidable TSMC is than a node that ran like a dream (such as N5) could ever show. As they say your true mettle is shown in times of crisis.

 

[MKWVentures]

Is Intel doing better on Intel 3 than N3B cause here is one leak from Twitter I don't know what DD 0.15 means here but he says for same die yield of Intel 3 is close to that of Intel 7

Intel is not shipping Intel 3 to end customers (server buyers) yet so we do not have teardown. Intel may ship TSMC N3 before Intel3 to end customers.

yield numbers are not correct as of today. using D0 yield equation is not useful for bleeding edge nodes (failures are not random defects). I am pretty sure TSMC and Apple know what they are doing since they are fairly successful at this stuff LOL.