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[FONT=Helvetica, Arial, sans-serif]What are your views regarding pure analog IP and custom analog designs under 30nm and below? As a mixed analog digital - designer ( big A little d), can we still use analog techniques such as folded cascodes, simple differential amplifiers with active loads, current source biasing etc.? Would more use of depletion devices instead of enhancement devices be more effective here? [/FONT]
[FONT=Helvetica, Arial, sans-serif]How about input and output common mode range? Does combination parallel NMOS and PMOS differential inputs make sense? Are there other differential input topologies which allow for full ground to Vdd common mode range? For outputs, common drain/common source outputs seem to make sense here. Are there totem pole output topologies that works here for full gnd to Vdd output range?
Seems that obtainable ring oscillator frequencies of ~200GHz for inverters using ~30nm line widths point to comparators with 5ps response times (for a 5mV overdrive with 100mV step) or op amps with unity gain bandwidths of ~20GHz? [/FONT]
[FONT=Helvetica, Arial, sans-serif]Your comments and links appreciated. [/FONT]
That's a very broad set of questions about using analog IP for 28 nm and smaller nodes. Just searching SemiWiki for "analog" produces several hundred results.
I am a device engineer and this is my understanding from my interactions with circuit designers and not a first hand experience. Hope it helps.
There is nothing fundamentally wrong in designing analog ip in 28nm and below. Virtually any chip has some analog blocks. My understanding is that you are looking at analog intensive applications though. There are a few drawbacks of designing analog blocks in deeply scaled technologies. Passive elements typically don't scale much. If you aim for a higher frequency or your ip is not dominated by passives you can justify a smaller node. Otherwise your total chip area will not scale evenif your transistors are smaller.
For analog blocks that require relatively high transistor gain (gm*ro), analog designers often stick to Lg much larger than the minimum allowed. Something above 100nm is very common. This is because output resistance degrades as you make Lg small. From the output characteristics of the transistor you can see this as a sloped Id-Vd in saturation, someting device folks refer to as DIBL (although measured from Id-Vg). A technology with smaller DIBL and thus flatter Id-Vd, offers higher gain. So it would be possible to use smaller gate length and still get reasonable gain. For example, we showed that FDSOI devices with a gate length of about 40nm give a gain comparable to what you get from a 150nm bulk planar device. Once you scale Lg you can scale W in proportion and also enjoy from higher ft and fmax of shorter Lg.
The other typical barrier is device mismatch which forces designers to use wider devices than they would otherwise need. That simply translates to higher power dissipation. Again a technology with smaller mismatch helps.
Finally, gate voltage overdrive drops as you scale the technology. For a 28nm technology with max Vdd of about 1V and Vt of 0.4 V, there is not much left to stack transistors. Folding is a must, but not sure even if that gives you enough headroom. Complimentary stages have their own drawbacks, but with the typical Vt and Vdd even those do notprovide enough room. You need a low Vt transistor and it's not available. I have seen people reorting to thicker oxide devices in the technology so that they can go to 1.5-1.8V or even 3V, but that defeats the purpose of using s smaller node for analog dominated circuits. Forward body biasing is a trick you can play, but in bulk devices you can only lower Vt by 50-100mV.
What are your views regarding pure analog IP and custom analog designs under 30nm and below? As a mixed analog digital - designer ( big A little d), can we still use analog techniques such as folded cascodes, simple differential amplifiers with active loads, current source biasing etc.? Would more use of depletion devices instead of enhancement devices be more effective here?
How about input and output common mode range? Does combination parallel NMOS and PMOS differential inputs make sense? Are there other differential input topologies which allow for full ground to Vdd common mode range? For outputs, common drain/common source outputs seem to make sense here. Are there totem pole output topologies that works here for full gnd to Vdd output range?
Seems that obtainable ring oscillator frequencies of ~200GHz for inverters using ~30nm line widths point to comparators with 5ps response times (for a 5mV overdrive with 100mV step) or op amps with unity gain bandwidths of ~20GHz?
From an EDA point of view, I see more designers relying on simulation tools for designing circuits in <65nm technologies. The traditional analog method of algebraic equation solving becomes more and more inaccurate and difficult with advanced node's second order effects, transistors in moderate inversion, low voltage design, or low power optimization. Impact of corners and mismatch grows, in some unexpected ways.
More extensive analog verification against parametric variation becomes a must-have. I see more designers using tools for sensitivity analysis and sizing/optimization in 28nm and below than in larger process nodes.
One of the key reasons for using native deep sub micron devices such as <28nm is to obtain wide bandwidth performance which scales with technology. Designing a ~0.1 to 1THz unity gain bandwidth op amp or a 1ps delay amplifier to implement direct analog processing of mmwave RF without the need of a THZ speed A/D. After all, number crunching 12Bit TB/sec word data would be a task unto itself.
Regarding matching, it is my understanding that in a 28nm process, a line widths of 28nm is kept to 28nm +/-10 % or 25nm to 31nm variation. As such, it is my understanding that a geometry drawn at 280nm in a 28nm process will be kept to 280nm ~+/-1%, a geometry drawn at 2.8um will be kept to 2.8um ~+/-0.1%, etc. Also, interdigitating devices, implementing well known common centeroid structures at greater than minimum dimensions should help here. As I see it, there is really no practical limit to obtaining high accuracy matching, and there are trim techniques -- binary weighted fusible links -- or flash memory cells here.
The last time I used extensive algebraic equation solving to resolve analog circuit design issues was many moons ago. All of my IC designs are 100% simulated with expected internal and external parasitics -- capacitances, resistances, and inductances. Especially in switch-mode circuits, I use extracted bond wire parasitics inserted in the simulation. Wherever I expect significant voltage gain, all of the devices in the gain path are checked during simulation to see that they are operating in the weak inversion region. Certainly, during transient step simulations, I expect my devices to temporarily go into the linear region. Also, at a minimum, I simulate worst case corners for process, inputs, Vdd supplies, and external loads (both minimum and maximum loads.)
I have also used sensitivity analysis tools. However, I view any of my circuits being sensitive to parametric shifts as candidates for re-design/re-layout.
I agree, a motivation to use smaller gate length is to work at higher frequencies. A typical 28nm node device should give you an ft/fmax of around 300GHz. Below 28nm, they most likey flatten or drop.
One component of mismatch is random dopant fluctuation. For a typical 28nm device and W=1um sigma Vt just coming from RDF is > 15mV.
Matching is difference between two transistors close to each other. The +/-10 % variation on line widths is not such an effect; if a poly line is off the one next to it likely is also off with almost the same offset. Short range matching is determined by things like random dopant fluctuations, line width roughness, etc. These effects typically don't scale with scaling of the widths but have to be improved by process optimization or even using undoped channels.
I agree with you both regarding 28nm devices in a 28nm process, and I also trust that you know what you are doing. However, a pair of devices W/L=1000um/100um will match better in this hypothetical 28nm process than the same device pair in a 100nm process. A pair of 100nm wide diffused resistors, created in a 28nm process will also match better than the same pair created in a 100nm process.
Would not the existence of pairs of W/L=1000nm/28nm devices with measured sigma Vt of >15mV in this 28nm process point to the expectation of pairs of W/L=2000nm/56nm devices with sigma Vt <15mV or less?
Certainly, I fully expect well known common centeroid, interdigitation layout techniques will be used throughout to optimize matching. I also recognize the strategic placement of dummies, device orientation, and piezoresistive effects -- all affecting matching.
Khaki, please let me know why you expect the flattening of ft/fmax below 28nm? What physical mechanisms are coming into the picture here that was not present or of no consequence/ignored in technologies above 28nm?
Ok, my first comment was based on the assumption that cost is a factor here. If not, it is possible that a transistor with a given W and L have better characteristics in say 28nm node vs say 130nm. For example, the thin oxide device will have higher gm, but of course higher Cg. Whether the net is an improved performance depends on your application and exact parameters. However, I would be catious in saying the same dimensions in general have smaller variation in a smaller node. The litho and etch process are optimized for the short Lg and as long as longer Lg is printed ok, people will live with it. Consider the case of 28nm vs 20nm, both using the same immersion litho to print gate. The 20nm node needs to push litho harder and in doing so will end up with worse conditions for long or wrong way gates. Consider Intel's 14nm now. Short Lg is printed by sidewall image transfer, but it only gives you one Lg. Meaning that longer Lg need to resort to the same immersion litho that they used in say 32nm.
What I mean here is that I cannot give a general rule of thumb that a given transistor is always better registered in a smaller node.
Similar arguments can be made for other parameters. For example in tuning the Vt of the shortest Lg it is possible that longer Lg in a smaller node end up with higher Vt than the same Lg in an older technogy. Something that analog designers in general hate.
Of course, you'll rely on models from foundry and extensive simulation. But then one thing I've heard many times is generally older technologies are characterized much better for parameters that analog designers care about as well as matching, variation, etc. this is just because more people used them. How well the models capture Si is probably the most important factor in deciding which node suits your application.
Agreed, there probably are no generalized rules here. As an analog designer, I make it a point to, .. at the very least, obtain a high level understanding of the lithos, the devices, the optics, and the physics involved in pressing the limits.
I do rely on models provided by the foundry, and certainly simulate 100% of my designs using them. I also do what I can to obtain test patterns from the foundry so that I can do lab bench curve tracer plots and verify device characteristics such as Vt shifts for Lg greater than the minimums, and overall wafer Vt consistency with respect to die position. In fact, even if my immediate need doesn't exist for the most advanced process node, I go out of the way to continue to design within a process node no older than 10yrs.
Regarding Vt, I prefer depletion devices when available. When properly designed, differential NMOS depletion input device circuits can include ground in its common mode input range. In fact, this same differential NMOS depletion input circuit can be modified to also include Vdd in its input common mode range. Shorting its gate and source creates a simple current source from a depletion device as well.
I prefer to work with a foundry that can not only provide accurate models but one that provides its customers access to its key process and device engineers.
For critical circuits, I design my own custom devices with the information provided by the foundry to extract maximum bandwidth, lowest noise, best input matching, or best power dissipation. In fact, the only time I use devices or IP provided by the foundry are in non-critical circuits or logic where overall costs, and accuracy of CAD layout implementation is of primary importance.
I agree with you both regarding 28nm devices in a 28nm process, and I also trust that you know what you are doing. However, a pair of devices W/L=1000um/100um will match better in this hypothetical 28nm process than the same device pair in a 100nm process. A pair of 100nm wide diffused resistors, created in a 28nm process will also match better than the same pair created in a 100nm process.
I was just focusing on the matching part of the equation as people mentioned here the +/- 10% variation; not on the analog performance between nodes in general.
As an analog designer you likely know the Pelgrom constant for beta and Vt; e.g. the relation between the variability of on-current and Vt to the square root of the area of a transistor. Improvements in the processing means this parameter scales with technology but not as fast as the gate density for digital. This means that you don't get the same area scaling for matching sensitive circuits as for digital logic and thus not the same cost advantage with scaling. Additionally NRE cost for smaller nodes is going up.
I have used Pelgrom constants and I also am aware that as device nodes get smaller, the variability and scaling for matching does not scale as well. I believe it has something to do with the basic atomic size and structure of crystalline silicon getting into the way.
Regarding analog circuits not scaling in density, this is also true but much of the lack of scaling has to do with obtaining and getting better performance and additional features. Speaking as an experienced new product analog design engineer, why design something someone else has created unless one can implement one that is better -- wider bandwidth, higher speed, lower noise, lower power, etc.. With the advanced nodes, and with some effort and creativity, one can achieve and create a product others have not done yet... This is the attraction of going to the more advanced nodes for me.
Regarding analog circuits not scaling in density, this is also true but much of the lack of scaling has to do with obtaining and getting better performance and additional features. Speaking as an experienced new product analog design engineer, why design something someone else has created unless one can implement one that is better -- wider bandwidth, higher speed, lower noise, lower power, etc.. With the advanced nodes, and with some effort and creativity, one can achieve and create a product others have not done yet... This is the attraction of going to the more advanced nodes for me.
This morning, I had a chat with one of the 60GHz guys here at imec and he says that they are using 28nm for the main reason that in the end the blocks are made to be integrated on a SoC where the digital part is still scaling. For them they would have the same performance if they would use 40nm and it would be cheaper also.
I am sure your chat with the 60GHz guys are right on, and are in all probability 100% correct. I also know that there are a lot of analog which doesn't need performance that intelligent scaling may provide so that 28nm is no more advantageous than 40nm. However, if the SoC part of the chip requires 28nm, there is no point in staying at the 40nm design rules -- it will consume 100% more area of a more expensive piece of silicon. One must consider costs as well.
I cannot predict with certainty what analog cells/IP/circuits may benefit from scaling, but my guesses are:
1. RF bandwidth (>10Giga samples/sec) high resolution (>12Bits) Analog to Digital Converters, with full auto-calibration.
2. Millimeter bandwidth ( >100Giga Points/sec) high resolution (>12Bits) Digital to Analog Converters, with full auto-calibration.
3. Millimeter bandwidth, (>1THz), high accuracy (better than .01%) analog multipliers, with digital calibration.
I am also certain the above are being worked on today in various research circles. We just don't hear about them until their projects are completed and published or produced.
