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10nm: Intel vs. TSMC

Morris Zhang: Moore's law is Coming to an end

"TAIPEI, Taiwan — Morris Zhang, Chairperson of the Taiwan Semiconductor Manufacturing Company (TSMC), has been honored with a Visionary Award by an international organization on Thursday. He pointed out that the Moore's law will face a great challenge as soon as the advanced process stepped into the 7mn process."

Dec 5, 2014
CTIMES News - Morris Zhang: Moore's law is Coming to an end
 
We should define "volume manufacturing" as when Apple ships a notebook (Intel) or sub-notebook (tablet/smartphone) in a given technology node. By that definition, 14nm is not in volume manufacturing yet; 20nm is in volume manufacturing since October 2014. Note that Apple can't meet demand for the iPhone 6 today (December 2014), which led CNBC to ask an interesting question: Why can't Apple meet demand for the iPhone 6?.
 
benb said:
By that definition, 14nm is not in volume manufacturing yet; 20nm is in volume manufacturing since October 2014.
Click to expand...

I agree that Intel’s 14nm is not at high volume production - yet. The process is probably still struggling with yields.

benb said:
Note that Apple can't meet demand for the iPhone 6 today (December 2014), which led CNBC to ask an interesting question: Why can't Apple meet demand for the iPhone 6?.
Click to expand...

American media loves to report scandals, riots, disasters, AND - iPhone.

Apple has truly succeeded: now you look outdated if you don’t own a latest iDevices.
 
user_2013101 said:
I agree that Intel’s 14nm is not at high volume production - yet. The process is probably still struggling with yields.
Click to expand...

This is no longer true. Portland is in HVM. Chandler will be HVM in Q1 and Dublin in Q2. The yield problem has been solved so Intel 14nm CPUs will be flooding the market next year. No sign of the Intel SoCs (Broxton or Cherry Trail) as of yet though. I'm talking about Silicon not PPT slides.
 
Daniel Nenni said:
Chandler will be HVM in Q1 and Dublin in Q2
Click to expand...
Well, for F24 in Ireland, it will be a very hard time. They have very clever engineers, but they are jumping from 65nm directly to 14nm.
I wish them all the best, but it is not going to be a very easy ramp. I really hope to be wrong.
 
astilo said:
Well, for F24 in Ireland, it will be a very hard time. They have very clever engineers, but they are jumping from 65nm directly to 14nm.
I wish them all the best, but it is not going to be a very easy ramp. I really hope to be wrong.
Click to expand...

Intel does "copy exact" so I hope it is a smooth transition. I do know people there so I will probably hear about it if it is not. There had been rumors of that fab shutting down so this really is good news!
 
Daniel Nenni said:
This is no longer true. Portland is in HVM. Chandler will be HVM in Q1 and Dublin in Q2. The yield problem has been solved so Intel 14nm CPUs will be flooding the market next year. No sign of the Intel SoCs (Broxton or Cherry Trail) as of yet though. I'm talking about Silicon not PPT slides.
Click to expand...

Thanks for the info. Based on the above statements, assume true, in terms of time-to-market, Intel’s 14nm has roughly 6 months of leads over TSMC’s 16FF+. In terms of CPU benchmarks, Intel processors may have some advantages. In terms of integrated mobile SoC, Intel is still behind. In terms of density, it does not look promising for Intel, either, even though density may improve beyond the Core-M in the subsequent 14nm chips.

Overall, the deliberately-created perception, that Intel enjoys 3+ years or a few nodes of leads, is not true. At best, Intel has minor leads in the process technology.

However, I don’t expect Intel’s PC/server domination to change in the next 3-5 years, despite some attempts of ARM-based servers by AMCC, AMD, QCOM, etc.
 
According to ASML, TSMC may introduce EUV into 10nm production mid-node, or use EUV on 7nm. So far, TSMC seems to be the biggest buyer and the first adopter of EUV.

Dec 8, 2014
TSMC to Use EUV for 7nm, Says ASML | EE Times



12-08-2014
TSMC Bringing EUV Into Production

The initial PDKs for 10nm are already out and they involve multiple patterning.
...
In fact ASML's CEO Peter Wennink confirmed this:
We are working with a customer [presumably TSMC] towards a mid-node insertion of EUV at the 10nm logic node expected in late 2016. Other customers are preparing for initial learning in a manufacturing environment.

https://www.semiwiki.com/forum/content/4089-tsmc-bringing-euv-into-production.html
 
Last edited:
Please note that I have no prediction if or when EUV can be used in volume production economically. I cited those EUV developments to indicate the latest attempts by ASML and TSMC. In my opinion, the result remains uncertain.

Due to numerous technical hurdles, EUV has been delayed for many years, despite tens of billions of investment. Both Intel and foundries had developed ways to do 10nm without EUV.

It should be considered a major breakthrough when EUVs finally work out in actual volume production.
 
Last edited:
[h=4]Latest of TSMC 10nm progress[/h]

Page 33 of transcript from Jan 15’s TSMC investor conference:

Click "Earnings Conference Transcript"

Roland Shu- Citigroup - Analyst
Thanks. Just a 10-nanometer question to C.C. Since, C.C., you said we are expecting to volume production of 10-nanometer in 2017. But I remember in the past two quarters actually our goal was to pulling in 10-nanometer mass production by end of 2016. So are we pushing out the 10-nanometer mass production schedule a little bit on that?

C.C. Wei- TSMC - President and Co-CEO
Let me explain that, because 10 nanometer, the mask layers is about 70 to 80. So you've got to start in 2016 to have output in 2017. So what I'm talking about is 2017 is to start to have revenue.
Click to expand...

It’s vague when in 2017 the 10nm is to contribute to revenue. If 1Q17, then the 10nm volume production ramp must start no later than 3Q16, perhaps even 2Q16.
 
user_2013101 said:
It’s vague when in 2017 the 10nm is to contribute to revenue. If 1Q17, then the 10nm volume production ramp must start no later than 3Q16, perhaps even 2Q16.
Click to expand...

The 10nm PDKs are just now coming out starting with version .01 so it really is too early to make a qualified assessment. Manufacturing is one challenge, design is the other. 10nm will take some serious design considerations with quad patterning or full coloring or a variety of other issues. If you look at the Apple SoC business with a much higher level of integration, 2017 is an aggressive prediction for 10nm. Could easily be 2008. My opinion.
 
Daniel Nenni said:
The 10nm PDKs are just now coming out starting with version .01 so it really is too early to make a qualified assessment. ...
Click to expand...
I agree that the 10nm timetable is unusually aggressive, to the point that I am somewhat skeptical.

On December 14, 2014, I wrote:

"TSMC has reiterated multiple times its 10nm schedule, which is insanely aggressive ...

"Either TSMC has set itself up for a humiliating disappointment.

"Or, purely out of my own speculation, perhaps TSMC has developed some sort of unannounced breakthroughs, as innovative and pivotal as immersion it invented before,"

https://www.semiwiki.com/forum/f293/misinformation-intel-tsmc-4952-post17312.html#post17312
 
user_2013101 said:
I agree that the 10nm timetable is unusually aggressive, to the point that I am somewhat skeptical.
On December 14, 2014, I wrote:
"TSMC has reiterated multiple times its 10nm schedule, which is insanely aggressive ...
"Either TSMC has set itself up for a humiliating disappointment.
"Or, purely out of my own speculation, perhaps TSMC has developed some sort of unannounced breakthroughs, as innovative and pivotal as immersion it invented before,"
Click to expand...

Here is how it works:

TSMC sets targets hand-in-hand with customers and partners in regards to power, performance, area, yield, delivery dates, and capacity. It is a trade-off juggling act with lots of balls in the air. 28nm was a challenge because of HKMG. 20nm was double pattering. 16nm is FinFETs. According to the experts I have met at the recent conferences the 10nm challenge was lithography and that has been solved without EUV. Once implementation starts there will be bumps and delays the question is how big and how long?

Intel really hit some bumps with 14nm but that learning will serve them well at 10nm. TSMC took a more conservative approach with 20nm and 16nm and avoided the big bumps which will also serve them well at 10nm.

TSMC does quarterly if not monthly reviews with early access customers and partners so the balls stay in the air but no matter how well you plan new process yield problems can happen and they generally do. Before Apple, product delivery dates could be pushed out but now it is yield or die and TSMC people worked around the clock (both on and off site) to get 20nm out. It truly was an amazing feat and the financial reward is well deserved.

16/14nm is done and will make it in time for the 2015 Fall iProduct refresh. 10nm has started implementation and could certainly be done in time for fall 2017 product refresh. The question is who will do the 2016 iProduct refresh? Will TSMC reclaim FinFET dominance? TSMC certainly thinks so but Samsung disagrees. Time will tell. Those contracts have not been signed yet.
 
LinkedIn said:
...
The question is who will do the 2016 iProduct refresh? Will TSMC reclaim FinFET dominance? TSMC certainly thinks so but Samsung disagrees. Time will tell. Those contracts have not been signed yet.
Click to expand...

Thanks for providing some detail info.

Not surprisingly, due to the pervasive media assaults, it appears that you assume Samsung had won most or all of A9 orders this year. Such perception may be more of the result of Samsung’s PR offensives, instead of the reality.

I had written quite a bit on this subject, under another thread, linked below. I may or may not be correct, but perhaps an alternative view is worth consideration.

https://www.semiwiki.com/forum/f302/tsmc-tsm-q4-2014-results-dicscussion-5334.html
 
user_2013101 said:
Thanks for providing some detail info.

Not surprisingly, due to the pervasive media assaults, it appears that you assume Samsung had won most or all of A9 orders this year. Such perception may be more of the result of Samsung’s PR offensives, instead of the reality.

I had written quite a bit on this subject, under another thread, linked below. I may or may not be correct, but perhaps an alternative view is worth consideration.

https://www.semiwiki.com/forum/f302/tsmc-tsm-q4-2014-results-dicscussion-5334.html
Click to expand...

The consensus in Silicon Valley is that Samsung 14nm will be used for the A9 and TSMC 16nmFF+ used for the A9x. I do not consider press releases as part of my expert opinion process, especially ones from Korea.
 
Article on Intel’s 10nm progress, or lack of progress?

During Intel's investor meeting in 2013, CEO Brian Krzanich showed the following slide: ...Intel expected to have its 10-nanometer manufacturing technology in production by the end of 2015.
...
A year later, at its November 2014 investor meeting, Intel didn't say much about its 10-nanometer production timelines.
...
The company already disclosed its initial plans for 10-nanometer in 2013, and I don't think there's much chance it will accelerate its plans there.

January 26, 2015
Intel Corporation is Being Awfully Quiet About 10-Nanometers (INTC)
 
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