Apple A17Pro transistor density

[Fred Chen]

The transistor density on an N3 (specifically N3B) product is already available:

https://twitter.com/i/web/status/1711453511848706228

So the Bionic chip density scaling rate is lower at beginning of N3 compared to beginning of N5.

 

[Daniel Nenni]

N3B is not an optimized node. Compare 5P with 3P is you want an apples-2-apples comparison, right?

 

[Fred Chen]

A18 is to be released next.

 

[DaRAGingLunatic]

Ouch.
Estimated Yield rate only 50-60%. Thats with an -8.8% die space compared to A16 Bionic.
-30% to -40% less yield than A16 Bionic.
Yield 50%-60%...

With a 1cm^2 die.

Throwing away 40-50% of the wafer, at $20k each wafer?

TSMC this is a not a good look for 3nm. You need those High NA EUV machines asap.

 

[Fred Chen]

You need those High NA EUV machines asap.

That would make things worse, etching with thinner resist. New versions of N3 still spinning out.

 

[siliconbruh999]

Ouch.
Estimated Yield rate only 50-60%. Thats with an -8.8% die space compared to A16 Bionic.
-30% to -40% less yield than A16 Bionic.
Yield 50%-60%...

With a 1cm^2 die.

Throwing away 40-50% of the wafer, at $20k each wafer?

TSMC this is a not a good look for 3nm. You need those High NA EUV machines asap.

Is Intel doing better on Intel 3 than N3B cause here is one leak from Twitter I don't know what DD 0.15 means here but he says for same die yield of Intel 3 is close to that of Intel 7

 

[Mooredaddy]

Ouch.
Estimated Yield rate only 50-60%. Thats with an -8.8% die space compared to A16 Bionic.
-30% to -40% less yield than A16 Bionic.
Yield 50%-60%...

With a 1cm^2 die.

Throwing away 40-50% of the wafer, at $20k each wafer?

TSMC this is a not a good look for 3nm. You need those High NA EUV machines asap.

where are you getting these numbers. This is not what i've heard at all

 

[Fred Chen]

where are you getting these numbers. This is not what i've heard at all

It's from the posted source, from eight months ago.

 

[hskuo]

Is Intel doing better on Intel 3 than N3B cause here is one leak from Twitter I don't know what DD 0.15 means here but he says for same die yield of Intel 3 is close to that of Intel 7

intel 3 DD less than 0.15? If it is true, I will blame Pat G to be too conservative to mass production intel 3. Even for tsmc, it will take at least 3-4Q to reach that level after risk start.
Hi NA EUV is not production ready and has low single digit pre=production tools available.

 

[hist78]

The transistor density on an N3 (specifically N3B) product is already available:

https://twitter.com/i/web/status/1711453511848706228

View attachment 2001
So the Bionic chip density scaling rate is lower at beginning of N3 compared to beginning of N5.

How did the author come out the 50~60% estimated yield?

 

[hskuo]

‘Better Yield on 5nm than 7nm’: TSMC Update on Defect Rates for N5

www.anandtech.com

 

[siliconbruh999]

intel 3 DD less than 0.15? If it is true, I will blame Pat G to be too conservative to mass production intel 3. Even for tsmc, it will take at least 3-4Q to reach that level after risk start.
Hi NA EUV is not production ready and has low single digit pre=production tools available.

Can you please tell me what will that translate into yield % an approximation https://x.com/OneRaichu/status/1798678499747836002 here is the tweet link btw

 

[hskuo]

Can you please tell me what will that translate into yield % an approximation https://x.com/OneRaichu/status/1798678499747836002 here is the tweet link btw

Don't be too lazy. Wafer CP yield is correlated to die size. There are lots of public info available. Here is one of them.

Chapter 20 TSMC 5NM Yield analysis Dr. Wei-E Wang ppt download

Yield Limiters Contaminants (used to be bad, now is somewhat resolved) Textbook formulae no longer applicable 3 ks.umass.edu/cgi/ viewcontent.cgi?r eferer= w.google.com/&h ttpsredir=1&articl e=1863&context= theses TSMC 5NM

slideplayer.com

 

[mattyenright]

That would make things worse, etching with thinner resist. New versions of N3 still spinning out.

Direct self assemble in conjunction with NA-EUV perhaps?

 

[Fred Chen]

Direct self assemble in conjunction with NA-EUV perhaps?

High-NA results in ultrathin, too thin etch masks (10 nm). DSA has some randomness of its own, but still under study.

Cut redistribution, self-aligned vias might be on the table.

 

[milesgehm]

It's from the posted source, from eight months ago.

All these yields are stated with such confidence in posts and original sources. IMO they are guesses and gossip.

 

[Fred Chen]

All these yields are stated with such confidence in posts and original sources. IMO they are guesses and gossip.

Usually I am suspicious as well. I had no yield expectations, I was after the 3nm transistor density.

 

[BruceA]

All these yields are stated with such confidence in posts and original sources. IMO they are guesses and gossip.

A small group at the fabless know. Few have direct visibility of multiple generations and x company but the end goal for all companies is simple enough, LOL

 

[Daniel Nenni]

where are you getting these numbers. This is not what i've heard at all

Not even close for today's numbers. Maybe this was last year pre Apple ramp?

 

[Fred Chen]

D0 must be >0.5 to have 50-60% so it would not be on a trend plot presented by TSMC such as above so this should be just starting out.