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Apple A17Pro transistor density

Fred Chen

Moderator
The transistor density on an N3 (specifically N3B) product is already available:
Bionic chip density trend.png

So the Bionic chip density scaling rate is lower at beginning of N3 compared to beginning of N5.
 
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Ouch.
Estimated Yield rate only 50-60%. Thats with an -8.8% die space compared to A16 Bionic.
-30% to -40% less yield than A16 Bionic.
Yield 50%-60%...

With a 1cm^2 die.

Throwing away 40-50% of the wafer, at $20k each wafer?

TSMC this is a not a good look for 3nm. You need those High NA EUV machines asap.
 
Ouch.
Estimated Yield rate only 50-60%. Thats with an -8.8% die space compared to A16 Bionic.
-30% to -40% less yield than A16 Bionic.
Yield 50%-60%...

With a 1cm^2 die.

Throwing away 40-50% of the wafer, at $20k each wafer?

TSMC this is a not a good look for 3nm. You need those High NA EUV machines asap.
Is Intel doing better on Intel 3 than N3B cause here is one leak from Twitter I don't know what DD 0.15 means here but he says for same die yield of Intel 3 is close to that of Intel 7
 

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Ouch.
Estimated Yield rate only 50-60%. Thats with an -8.8% die space compared to A16 Bionic.
-30% to -40% less yield than A16 Bionic.
Yield 50%-60%...

With a 1cm^2 die.

Throwing away 40-50% of the wafer, at $20k each wafer?

TSMC this is a not a good look for 3nm. You need those High NA EUV machines asap.
where are you getting these numbers. This is not what i've heard at all
 
Is Intel doing better on Intel 3 than N3B cause here is one leak from Twitter I don't know what DD 0.15 means here but he says for same die yield of Intel 3 is close to that of Intel 7
intel 3 DD less than 0.15? If it is true, I will blame Pat G to be too conservative to mass production intel 3. Even for tsmc, it will take at least 3-4Q to reach that level after risk start.
Hi NA EUV is not production ready and has low single digit pre=production tools available.
 
intel 3 DD less than 0.15? If it is true, I will blame Pat G to be too conservative to mass production intel 3. Even for tsmc, it will take at least 3-4Q to reach that level after risk start.
Hi NA EUV is not production ready and has low single digit pre=production tools available.
Can you please tell me what will that translate into yield % an approximation https://x.com/OneRaichu/status/1798678499747836002 here is the tweet link btw
 
Can you please tell me what will that translate into yield % an approximation https://x.com/OneRaichu/status/1798678499747836002 here is the tweet link btw
Don't be too lazy. Wafer CP yield is correlated to die size. There are lots of public info available. Here is one of them.
1718080521666.png

1718080374410.png
 
Direct self assemble in conjunction with NA-EUV perhaps?
High-NA results in ultrathin, too thin etch masks (10 nm). DSA has some randomness of its own, but still under study.

Cut redistribution, self-aligned vias might be on the table.
 
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All these yields are stated with such confidence in posts and original sources. IMO they are guesses and gossip.
A small group at the fabless know. Few have direct visibility of multiple generations and x company but the end goal for all companies is simple enough, LOL
 
D0 must be >0.5 to have 50-60% so it would not be on a trend plot presented by TSMC such as above so this should be just starting out.
 
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