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Advanced CMOS Technology“Intel 18A Platform Technology Featuring RibbonFET (GAA) and Power Via for
Advanced High-Performance Computing
” – Intel (Paper T1-1)
An advanced Intel 18A technology featuring RibbonFET and Power Via provides over 30%
density scaling and a full node of performance improvement compared to Intel 3. Intel 18A
offers high-performance (HP) and high-density (HD) libraries with full-featured technology
design capabilities and enhanced design ease of use.
Figures：(Left)Intel 18A vs. Intel 3 PPA (Power, Performance, Area) comparison (Right)
Intel 18A vs Intel 3 High Density Library, High Performance Library
Very nice. It looks like a >= 10:1 voltage droop reduction.. That should help a lot with both mobile/lower power threshold voltages and higher end desktop/workstation performance.. (Overclockers will love this)
FWIW the top frequency part shipping on Intel 3 is 4.3 GHz; though that is +0.1GHz above the previous gen server product on Intel 7. I'm curious what 18A will do for server part frequency in the future.
Very nice. It looks like a >= 10:1 voltage droop reduction.. That should help a lot with both mobile/lower power threshold voltages and higher end desktop/workstation performance.. (Overclockers will love this)
FWIW the top frequency part shipping on Intel 3 is 4.3 GHz; though that is +0.1GHz above the previous gen server product on Intel 7. I'm curious what 18A will do for server part frequency in the future.
Very nice. It looks like a >= 10:1 voltage droop reduction.. That should help a lot with both mobile/lower power threshold voltages and higher end desktop/workstation performance.. (Overclockers will love this)
Maybe I don't understand what you are saying but the Vdroop isn't super useful for low voltage (like Xeons or most leading edge foundry customers) situations. The bigger benefit is for reducing high V heat/power (desktop and laptop CPUs); at least that is my understanding. Low threshold voltage operation is a device property and is helped by things like lower leakage to help offset the smaller V wall between off and on at that low Vt. Meanwhile the Vdroop is a measure of how much voltage you are losing from electrical resistance in the metal stack. So that improvement is expected from BSPDN and isn't particularly special. Based on the thermal situation with BSPDN I would need to see actual products to make the determination if desktop and OC parts would like 18A. I suspect they won't because those parts have ultra high thermal density. I suspect 18A's sweet spot would be low voltage/low thermal density HPC (server CPUs and GPUs). But maybe the leakage will be too high for it to be perfect for that and maybe it is more comfortable with laptops where it is high voltage but thermal density isn't at surface of the sun levels so Intel's BSPDN thermal mitigations can handle it.
FWIW the top frequency part shipping on Intel 3 is 4.3 GHz; though that is +0.1GHz above the previous gen server product on Intel 7. I'm curious what 18A will do for server part frequency in the future.
That isn't a particularly useful comparison. Ignoring the design having a bigger impact on Fmax than process angle that I have discussed before: Many Xeons operate near Vmin to minimize power consumption per core so core count can be maximized. If you have any extra power budget after you bump up code counts and your non core parts of the SOC, then you can throw it at frequency. Typically when looking to understand the figures of merit for a new server chip on a new process I would look to find either a normalized core count or normalized power part. From there look at the opposite statistics and what the base frequency is.
As an example GNR and EMR both have a 64c sku. The GNR one runs at 330w at 2.4GhZ base. The EMR equivalent runs at 350w at 1.9 GhZ base. So the EMR is running at 1.34 C*V^2. Or in other words the i3 part must be running at significantly lower voltages even though it is running with slightly lower power and hilariously higher base frequency. And that is with a worse memory subsystem, accelerators, fewer sockets supported, and fewer dies.
Another example is again using Xeon 8592. 350w 64c and 1.9GhZ. Meanwhile 6788P is also 350w, 86c 2Ghz. Taking into account that iso process 6788 should be consuming an extra 5% per core at iso V for the frequency bump, the Intel 3 Xeon lowered power consumption per core by a whopping 71%.
Not perfect extrapolations to the Intel 3 performance/power entitlment but it gives you an understanding of magnitude of improvement based on the figures of merit that designers care about (TCO, power per core, and workload efficiency, etc).
Maybe I don't understand what you are saying but the Vdroop isn't super useful for low voltage (like Xeons or most leading edge foundry customers) situations.
My thinking process is that "many core" server farms spend a lot of time at idle or low power states. (As do Mobile devices of course where it matters perhaps more). Lower vDroop means more stable voltage upon load changes (at any power state), which should mean less worry about "idle stability" at lower voltages.
In practice, a processors idle / low frequency voltage is always set high enough so that when a core starts to ramp up, or receives more work than 'nothing', it can remain stable while executing and/or switching to/from idle states. Lower droop should mean a little more margin for that initial load spike impact on voltage. Thus, a chip with BSPD can probably reduce idle voltages at iso frequency.
