Intel announces 18A process node has entered risk production

[fansink]

What's the capacity of Intel Fab 52 starting 2026?

Fab 52’s capacity ramp is anticipated to begin at 1,000–5,000 WPM in late 2025, scale to 10,000–15,000 WPM in 2026, and reach a full capacity of 25,000–30,000 WPM by 2027–2028, assuming construction and yield targets are met.

 

[siliconbruh999]

I'm soooo glad you agree that Intel’s current 18A fabrication capacity is probably ~1,000 WPM, especially for risk production

No need to be sarcastic I was merely agreeing they will be doing 1K WPM for 18A but the actual capacity in Oregon is way higher than this even for D1X

 

[fansink]

No need to be sarcastic I was merely agreeing they will be doing 1K WPM for 18A but the actual capacity in Oregon is way higher than this even for D1X

Wafer fabrication capacities at Intel’s Ronler Acres campus in Hillsboro, Oregon, are 5,000–8,000 wafers per month for the D1X fab and 1,000–2,000 wafers per month for the D1D fab, totaling a combined capacity of 6,000–10,000 wafers per month, AFAIK, which in this case could stand to be further.

 

[nghanayem]

TSMC announced N2 risk production last year: https://ieeexplore.ieee.org/document/10873475

TSMC has to enter risk production sooner because they need to transfer process to HVM fab before HVM while Intel does HVM at the development site. And foundry customers will want a new product qual at the HVM site no matter how closely matched the HVM site is to the development site to minimize their risk (further extending how early risk production needs to happen in a foundry environment). I made a similar observation a couple of months ago with PDK 1.0 dates being within a quarter of each other despite 18A products launching around 3Q before N2 products. But this difference is why I say that Intel has alot of work to do in making sure the gap between process health and foundry readiness gets smaller. Because 18A vs N3P, slam dunk. 18A vs N2 not so much. 18A was HVM ready first, but for external customers N2 was effectively first.

1000 is wayyyy low it's fine for their risk production aslo Oregon's total capacity is 40K WPM iirc

1000 WSPM is like early pathfinding/exploration wafer volume (and probably too low even for that VERY limited use case), and is completely insufficient for process development. And you can forget the usual D1 HVM ramp. 1000 WSPM is 250 WSPW and 35 wafers per day. That is less than 2 lots per day. A single modern EUV scanner can run all 250W for the week in like an hour. Giving a utilization of around 0.6%. If that was all D1 ran, all of D1 would only need to be half maybe 1/2 or 1/4 the size of just D1C.

Based on the performance, Intel 18A is more like TSMC N3.

HD logic density seems that way, yes. Performance seems to be between N3 and N2. Even TSMC says 18A has better performance than N3P.

How many 18A wafers were they running before risk production and how many now? 5K per month? 10K?

10K is half of a modern logic fab. D1 is like 5 modern TSMC fabs in size (with 6 being a "gigafab" 100K+ WSPM). Granted, a development fab isn't fully optimized for maximum wafer outs, but let's say 50% for development and 50% for HVM, 20K WSPM for 5 fabs. No way. Way too small. Based on emissions, Techinsights determined that D1 is far more active than they expected so one would assume D1 isn't just sitting empty.

 

[MKWVentures]

How many 18A wafers were they running before risk production and how many now? 5K per month? 10K?

@nghanayem

""10K is half of a modern logic fab. D1 is like 5 modern TSMC fabs in size (with 6 being a "gigafab" 100K+ WSPM). Granted, a development fab isn't fully optimized for maximum wafer outs, but let's say 50% for development and 50% for HVM, 20K WSPM for 5 fabs. No way. Way too small. Based on emissions, Techinsights determined that D1 is far more active than they expected so one would assume D1 isn't just sitting empty.""

>>> So about how many 18A wafers were running before risk production and how many in risk production?

 

[fansink]

@nghanayem

""10K is half of a modern logic fab. D1 is like 5 modern TSMC fabs in size (with 6 being a "gigafab" 100K+ WSPM). Granted, a development fab isn't fully optimized for maximum wafer outs, but let's say 50% for development and 50% for HVM, 20K WSPM for 5 fabs. No way. Way too small. Based on emissions, Techinsights determined that D1 is far more active than they expected so one would assume D1 isn't just sitting empty.""

>>> So about how many 18A wafers were running before risk production and how many in risk production?

Either way, Intel's 18A is 4-6 months behind TSMC's N2, with the line of customers for N2 looking like the line for a Trump rally, and the line for 18A looking like a Biden rally.

 

[benb]

With a new production line, wafer starts are very low, and the line is long, and initially there are gaps in the line, so more starts fill the gaps until you have a decent coverage. This is why 1K-5K per month is a guesstimate, and not necessarily predictive of health. Many wafers get reworked, scrapped, lots get split up, experiments run, which makes the overall capacity, which assumes a steady state which definitely does not exist, just a made up number.

The above is all just standard semiconductor engineering. With 18A though there is a wrinkle; the advanced packaging is truly worthy of the name advanced. The BSPD process is being done in yet another facility I think, possibly New Mexico? So F52 and Mod 3 wafers aren't really complete until the BSPD facility completes them. That's where you would look for a clear signal of health I think. A steady capacity from the advanced packaging fab.

 

[Fred Chen]

With a new production line, wafer starts are very low, and the line is long, and initially there are gaps in the line, so more starts fill the gaps until you have a decent coverage. This is why 1K-5K per month is a guesstimate, and not necessarily predictive of health. Many wafers get reworked, scrapped, lots get split up, experiments run, which makes the overall capacity, which assumes a steady state which definitely does not exist, just a made up number.

The above is all just standard semiconductor engineering. With 18A though there is a wrinkle; the advanced packaging is truly worthy of the name advanced. The BSPD process is being done in yet another facility I think, possibly New Mexico? So F52 and Mod 3 wafers aren't really complete until the BSPD facility completes them. That's where you would look for a clear signal of health I think. A steady capacity from the advanced packaging fab.

It's true that Panther Lake is still partially 18A, there are still TSMC chiplets to be assembled with the 18A chiplet.

 

[nghanayem]

With a new production line, wafer starts are very low, and the line is long, and initially there are gaps in the line, so more starts fill the gaps until you have a decent coverage. This is why 1K-5K per month is a guesstimate, and not necessarily predictive of health. Many wafers get reworked, scrapped, lots get split up, experiments run, which makes the overall capacity, which assumes a steady state which definitely does not exist, just a made up number.

The above is all just standard semiconductor engineering. With 18A though there is a wrinkle; the advanced packaging is truly worthy of the name advanced. The BSPD process is being done in yet another facility I think, possibly New Mexico? So F52 and Mod 3 wafers aren't really complete until the BSPD facility completes them. That's where you would look for a clear signal of health I think. A steady capacity from the advanced packaging fab.

That isn't how BSPD works. It isn't advanced packaging. BSPDN is part of the wafer making process not the packaging process even though the underlying technologies are somewhat similar and employ some related manufacturing techniques. NM is for advanced packaging not 18A.

 

[siliconbruh999]

It's true that Panther Lake is still partially 18A, there are still TSMC chiplets to be assembled with the 18A chiplet.

Yes the IO Tile which they are reusing from Arrow Lake/Lunar Lake also a TSMC iGPU tile on one of the SKUs the IO tile is is approx 30 mm2 N6 this is very inexpensive compared to other things