Why is Trump Targeting TSMC? Expert Reveals the Hidden Agenda: "Saving Intel"

[Fred Chen]

I think you will start to hear the reality of what is going on at Intel foundry now that Pat is gone. No customers, Costs way to high, SCIP partnerships becoming problematic, Intel 3/4 losing money, 18A planning to lose money if they build fabs and lose money if they dont build fabs. There is a reason that Intel BOD is looking for options

"No customers"? That hasn't been reported yet. But the splitting of Intel has gotten much news this weekend for sure.

 

[blueone]

Americans are too prone to seeing hidden agendas everywhere. Some times things work as they appear on face value.

Much of this chatter is called freedom of speech, which doesn't exist for, I'm just doing some math in head, the majority of humans on the planet. However, your comment is basically a silly generalization and stereotype.

I've seen countless very expensive, and otherwise very intelligent consultants come to businesses, give big speeches, and then not coming with anything of value because there is really nothing to do, and the rut the business have found itself in, and particular problems are very plain, and simple. You cannot hire talents of the same level in the West with Taiwanese salaries, you cannot build cheap electronics outside of China if you need to import all BOM, and you cannot force assembly line workers to work past their biological limits. No bright Yale educated boy can fix issues of that kind.

Agreed.

Intel's problems are of this kind. Their process talent has left, or retired half a decade ago. Cultivating a new one takes 5-10 years. They don't have that.

How do you know that? Are you very familiar with Intel's process technical leaders, or are you just guessing based on your view of outcomes?

Intel will not start performing better if USA will tax Taiwanese chips even 1000%.

Superficially, I agree, but if a 1000% tariff were to materialize, Intel would get a huge amount of support from some very rich fab customers, like Apple and Nvidia. I'm not sure how that would affect the outcome, but I suspect very positively. However, the pain level until Intel could step up would be very high, because the turnaround wouldn't happen in a matter of months. Nonetheless, you've inadvertently brought up an interesting thought experiment.

 

[nghanayem]

That is a fair distinction. But I think my main point remains, Intel's historical approach to process design needs to change to meet the needs of an expanded clientele.

The large voltage range V-scaling usecase still needs to take a high priority, as Intel products will be the largest foundry customer for the foreseeable future. While unintuitive, I feel like splitting the company kind of makes this issue worse. An independent intel foundry needs to hold onto every major CCG die for dear life. If you have both companies under one CEO you can say, "Hey CCG you just got to accept that at the very least the initial process will be more heavily tuned for low V operation. Foundry needs to develop this to more easily secure additional external customers, and it better allows DCAI to scale xPU core counts. You must change your IPs and hardening to compensate for this new reality.". An independent foundry (be it Intel, TSMC, etc) would be unable to dictate terms with a customer. So I wonder if a fully independent Intel foundry will be put between a rock and a hard place on focusing optimization on lower power operation and offering the high V and high f support CCG wants. Ensure you keep your existing business or make a play to maybe expand to other customers (potentially at the expense of your bread and butter). While it feels bad, I feel like it would be hard to justify doing anything drastic enough to risk CCG's business.

I don't know if I explained this in a coherent manner because the idea only recently dawned on me. The more I think about it, this seems like it might have even happened to GlobalFoundries. They had a dual SOI and bulk process roadmap with the SOI SHP process leading, the bulk HP process trailing by a year, and the bulk LP process trailing even further behind. Having to maintain all of these extra development tracks couldn't have been cheap, even if we make the reasonable assumption that many of the innovations are re-useable. Besides the existing Chartered customers; GF took a very long time to get customers beyond ST-M dual sourcing for some extra capacity, AMD, and later IBM. All of these guys were big SOI fans with a fondness for high V and high f capability. Based on GF having a bulk HP and bulk LP path I can't imagine GF folks back in 2009 were thinking SOI was suitable for mobile or much of the industrial/auto/embedded markets. If you have the needs of AMD dictating what tradeoffs are made on your lead process offering, I guess it isn't hard to see why it would be difficult to swing QCOM from TSMC or MTK from UMC.

Would a bulk-LP first or only GF have had an easier time grabbing leading edge mobile contracts? Probably.
Would AMD have found a way to renegotiate their wafer agreements if GF wasn't providing them a suitable HP process? Maybe.
If AMD stuck with a bulk/LP only GF, would that have hurt AMD's product "competitiveness" and lower AMD's wafer demand? Definitely.

I'd be curious to see how things shake out for that alternative timeline GF that focused on a more broadly desirable process roadmap at the expense of making something "worse" for their current customers. Are things better, worse, or more or less the same?

I'm talking less about building capacity here and more about how you start wafers in the fab, and in that instance I think there is a subtle difference. Intel has frequently had to write down inventory over the years. I think it is safe to say that this is due to Intel's projections being overly optimistic. Intel's general philosophy seemed to be that they didn't want to leave a single potential sale on the table and could project demand over several quarters. I believe that this approach allowed for Intel's factories to start wafers earlier than they would have otherwise been able to and gave them more flexibility in running their fabs. This approach is what I am calling the build-to-projection model.

Now Intel is going to have customers come to them with orders for a very specific product on a specific delivery date as opposed to the more general orders placed by Intel products group that extend farther into the future. This is what I am calling the build-to-order model. Dealing with these specific product specific requrements will require Intel to run their fabs differently. Under the older, build-to-projection model, Intel could load their factories quite heavily, knowing how long the production tail was going to be. Factory physics says the price for heavy factory loadings is a reduction in velocity of individual lots through the fab in return for higher output. Running the fab slowly wasn't a problem as long as the output was there. On the other hand if you have very specific groups of lot that all need to move through the factory at a specific velocity, you don't have nearly as much flexibility in how you load your factory. That will be a paradigm shift for Intel.

Note that I'm not talking about specific commitments to run X number of wafers on the 18A process this year, but rather how you get specific lots through the factory on a specific timeline.

I see what you mean now. When Intel talked about cost savings identified by new accounting, they said some similar and some different things.

One similarity was yes in the old days Intel would have extra surge capacity so that money was never left on the table. Of course this practice very clearly stopped in the 14nm and 10nm eras where Intel was running at near 100% utilization for years and for bizarre reasons chose to outsource PCH dies and chipsets to Samsung rather than doing any number of forehead slapingly obvious things to the exisitng factory network (like move logic to China and give up on NAND when Micron JV ended, converting NM to more advanced process technologies, and filling empty fab shells literally anytime before 2020 instead of holding off so you don't have to start deprecating the buildings). Or even novel idea, build a new fab for the first time in a decade. Like oh I don't know one 450mm/EUV capabale D1X_mod 1 style mod at Israel and Ireland so that it isn't just OR and AZ with any fabs capable of EUV or 450mm (funny to think about today, but back then 450mm was still on the table during the realvent time period). Another similarity you mentioned was when you run a low mix of products, the velocity doesn't really matter as much as total output. As long as you have X wafers of raptor lake coming out of the fab per week, it doesn't really matter when that wafer was started (obviously some exceptions apply) since any two lots of raptorlake are completly interchangable with each other.

One difference was that the product division would rapidly oscillate their wafer start asks and cause alot of churn in the factories. There was also the comical volume of hot lots. I think they said it was 3x the volume and hurt total output by like 10%. So while the main production line was slowed to a crawl, Intel was seemingly good at hand holding a fairly large volume of lots quickly though the line to get all of those unplanned dash steppings and high demand products out.

I think the bigger thing that intel needs to make sure they can demonstrate world-class capability in the field of fab operations is tool health and wafer quality. If a Meteor lake lot gets scrapped not the end of the world, there are a whole lot of identical meteor lake lots that are right behind it. You scrap a one of a customer's 3 qualification lots, and you are in VERY DEEP doo-doo. Another major difference is at an IDM you want to save every wafer and every die. Any die that could have been saved but wasn't, isn't just the cost of the wafer but also lost revenue. Let's say you have a wafer abort inside an etch tool mid etch. At an IDM if it looks like it could be saved you would write a custom etch recipe to finish the etch. If it is saved; great, you saved the company alot of money. Maybe when it gets to assembly test it works just fine, maybe it performs a bit worse, or maybe it is totaly unsellable. The cost saving potetial often warrents giving it a try. At a foundry this doesn't fly. It comes down to whose risk this wafer is. For an IDM product and fab play for the same team, so it is both of their risk. They also have internal wafer sort so they will be able to make sure that wafer is good before shipping it out. For a fabless customer they send the wafer to an external OSAT with the foundry and OSAT having no collaboration. The fabless firm might even skip having the wafer sorted for cost saving reasons. If they take a suspect wafer, they are taking all of the risk on the wafer they paid the foundry being a dud after they pay an OSAT to take a look and maybe even risk sending defective material to their customers. For this reason foundry customers will never take suspect material. As a result of the wafer being the final product and not being able to sort test the wafers before handing them to the customer, foundries have to scrap anything that their own internal metrology cannot guarantee to be functionally identical to the customer's qualification samples. It is for this reason that IDMs have higher wafer yields (number of wafers that survive to the end of line) than foundries.

In this new world, Intel's wafer manufacturing arm now needs to make sure that they have sufficient in-line metrology to catch any issues without the aid of end of line testing even if Intel foundry and Intel products still are ok maintaining their business as usual "every die wants to live" operations. Inline metrology and first time right quality while always important are even more critical when Intel will be dealing with a higher mix lower volume environment where any tiny screw-up can wipe out most of a customer's in progress material, kill a PDK qualification lot, a testchip, or an NPI.

You make an excellent point. But if Intel is going to be a successful foundry they are going to have to cleary communicate their expectations on when a process is ready for external foundry producition as opposed to internal CPU products.

No-one I have ever talked to who has actually worked in a fab for a number of years has ever given the indication that Intel process health at ramp is as a rule of thumb is notably worse than TSMC at the beginning of process ramp. This is at least consistent with multiple instances where TSMC clearly came out of the blocks worse off. Examples off the top of my head include 22 vs 20 or 16nm, 45 vs 40nm, and 65 vs 65nm. But with that said, I suspect this is why Pat frequently mentioned Intel presumably always being the lead product (unless a customer really wanted to be the lead) and how Intel products would de-risk for external foundry customers. Either way, it isn't exactly like foundry customers can't just look at where the process is from a variation, different electrical parameters, performance as a % of the final performance target, and DD for said customer's testchip of choice. They can see exactly where in the process development lifecycle they are.

I think the more important area for improvement is how development is done. At TSMC, they focus on getting performance very close to the final target and accept that yield will improve more slowly for the time being. Once they get their performance architecture in place they can be confident that the changes needed from then on out are more evolutionary than revolutionary and fewer (if any) changes will occur that require significant (if any) design rework. From there they focus all effort on variation reduction (helps get those last few % of performance and improves yield) as well as an process changes to enhance die yield. It is also just efficent because instead of wasting time imrpoving yield just for your latest performance improvement to break it again you can focus on improving the yield on a mostly final process flow. Since fabless companies don't want to have to redo their homework or run new steppings due to some process change TSMC made. My understanding is that outside of the IP designers doing their thing, actual chip design tends to wait until the process more or less lock-in. If we take a look at 18A and N2, 18A will be ready first, and yet the anoucments for PDKs 0.9 and 1.0 for those two processes came out at a similar times with non Intel/Apple tapeouts happening in 2025. Granted, TSMC has been doing this for 40+ years and this is Intel's first rodeo. But it illustrates my point on something that needs to be improved over time. Another area I think needs improvement is being more restricitive early and loosening up later rather than the opposite. As an example with 10nm Intel said vias had minimum placement restrictions and beyond that a blank canvas in the sevice of designer hand tuning. For Intel 4 they talked about how they dropped that idea for a grid that vias must land in. Infinite layouts vs finite options make dealing with LLEs and process modeling easier. I also assume that fabless companies also just have no interest in any sort of "hand tuning" of layouts. For contrast look at TSMC N5. Even areas where your S/D contacts were not needed had to have dummy metal placed. Then on the more mature N5P and later you started to see less and less dummy metal. TSMC gives you a small sandbox that they can validate as for sure working. Then as they increase process margin and reduce variation they can expanded the sandbox. You can still stick to the old design rules and be safe, and if you change your design to the new looser design rules you can do so with the confidence everything will work per TSMC's process simulations.

Thank you for taking to time to clarify this for me. I second BlueOne's comment. Excellent post.

It is my pleasure. I love to learn and to share what I know.

 

[Fred Chen]

Intel first needs new leadership (CEO and BoD). How is this conspiracy theory with TSMC going to help that? How is gutting Intel R&D and manufacturing in favor of TSMC technology going to help Intel and the US? This seems absolutely ridiculous to me.

A much simpler approach would be to re host TSMC and make it a US based company and negotiate with China to keep TSMC independent after the Taiwan take-over. That is the deal of the century. The US could also make Taiwan a US territory like Greenland, Canada, etc... Or they could just rename it like the Gulf of Mexico.

A few days ago, I was just thinking how ridiculous this could get; I think that would be moving TSMC's Taiwan fabs.

 

[xman747]

I think you will start to hear the reality of what is going on at Intel foundry now that Pat is gone. No customers, Costs way to high, SCIP partnerships becoming problematic, Intel 3/4 losing money, 18A planning to lose money if they build fabs and lose money if they dont build fabs. There is a reason that Intel BOD is looking for options

So isn’t the solution to this something like - hey apple , meta , tesla. Have your chips created in the US or else. - D. Trump. All jokes aside - there is a lot of noise out there and I think it is just that. Intel needs a new CEO to stop this bleeding going on with the board. If this new CEO is any good - he will see the immense value in the foundry capabilities built over the last 3-4 years.Intel may very well be in the right place right time finally, with all this politics going on. Frankly Intel splitting would be a travesty business decision IMO. Most recent product launches have been good and new hands in the design pot will secure Intel some demand. Also: amazing users in this forum

 

[Artificer60]

No-one I have ever talked to who has actually worked in a fab for a number of years has ever given the indication that Intel process health at ramp is as a rule of thumb is notably worse than TSMC at the beginning of process ramp. This is at least consistent with multiple instances where TSMC clearly came out of the blocks worse off. Examples off the top of my head include 22 vs 20 or 16nm, 45 vs 40nm, and 65 vs 65nm. But with that said, I suspect this is why Pat frequently mentioned Intel presumably always being the lead product (unless a customer really wanted to be the lead) and how Intel products would de-risk for external foundry customers. Either way, it isn't exactly like foundry customers can't just look at where the process is from a variation, different electrical parameters, performance as a % of the final performance target, and DD for said customer's testchip of choice. They can see exactly where in the process development lifecycle they are.

I can't speak to TSMC, but I have heard from sources I consider reliable that 1) Intel has had initial ramps in the past at some truly marginal yields and 2) Intel yield improvement post ramp has diminished over the last few technologies. Though #2 may well be due to the challenges of quad patterning and the use of EUV may well set that ship right once Intel has moved down the EUV learning curve a bit. I'm very curious to see 18A and Panther Lake in the wild. Should be an interesting year.

 

[Fred Chen]

I can't speak to TSMC, but I have heard from sources I consider reliable that 1) Intel has had initial ramps in the past at some truly marginal yields and 2) Intel yield improvement post ramp has diminished over the last few technologies. Though #2 may well be due to the challenges of quad patterning and the use of EUV may well set that ship right once Intel has moved down the EUV learning curve a bit. I'm very curious to see 18A and Panther Lake in the wild. Should be an interesting year.

Intel started having the notorious yield issues at 14nm (before QP) so perhaps it is related to double patterning? They need to get that right, even when they have EUV.

 

[nghanayem]

I can't speak to TSMC, but I have heard from sources I consider reliable that 1) Intel has had initial ramps in the past at some truly marginal yields and 2) Intel yield improvement post ramp has diminished over the last few technologies. Though #2 may well be due to the challenges of quad patterning and the use of EUV may well set that ship right once Intel has moved down the EUV learning curve a bit. I'm very curious to see 18A and Panther Lake in the wild. Should be an interesting year.

I mean yeah. 14nm and 10nm were bungled, nobody would argue with you on that point. I was referring to "average" process technologies like 90nm, 45nm, intel 4/3, etc. Post ramp yield is a weird thing to say though given the ephemeral nature of things. The problem is by the time Intel was ramped they would be derampping (14 and to a slightly lesser extent 10 being exceptions). Comparing TSMC 90nm yields today verus intel 90nm yields back in 2007 when 90nm was brought offline is not a useful or relevant comparison. On the other hand, comparing 90nm DD 4 years after HVM start is a useful comparison. As for "post ramp" yield over the last decade, obviously it should be expected that intel 7 will always look worse for wear than N7 or N5 due to extra metal layers, MIM plates, and even beyond that the simple fact of FAR GREATER process complexity. For overall DD to be the same, intel's DD per layer would need to be dramatically lower than N7 and especially N5. Intel 14nm doesn't really have a TSMC comparison for yield 4 years after HVM start because 10FF (which also had poor initial yield) was taken out of production after two years and with the tooling converted to N7/6. What is certain is that in this day and age the current DD on 10/7 and 14 must at the very least be pretty darn good, given the 10s of millions of 700+mm^2 products Intel has sold on those processes over the better part of a decade.

 

[XtorTourist]

No he doesn't. Dave said Intel 7 cost to produce is less than TSMC price (if only barely) as evidenced by Intel 7 gross margin being single digit positive when priced vs a comparable TSMC process technology. He also said that 18A wafers aren't particularly more expensive to produce than intel 7 wafers, with ASPs 3X intel 7 wafers. You believe, if memory serves, that Intel 7 cost is over 2x TSMC price. And also for some reason that IF's operating loss cannot be explained by investment, R&D, and TWO simultaneous process ramps exceeding the meager operating income generated from poorly utilized Intel 7 fabs.

Do you have a link to where Zinsner said that Intel 7's cost was a bit less than TSMC's comparable node price?

 

[nghanayem]

Do you have a link to where Zinsner said that Intel 7's cost was a bit less than TSMC's comparable node price?

He verbally said Intel 7 margins were single digit with the new wafer pricing model one at least one of three occasions. It was either the investor meeting where they went over the model for the then upcoming finical break out of the manufacturing group, the meeting going over the recast financials, or the first earnings call after the recast financials. You can find the old transcripts for the presentations and the slide decks at intc.com. But the specific bit about intel 7 specifically being single digit was verbal rather than on a slide (as opposed to other comments about the average margin across across all pre-EUV nodes).

 

[Barnsley]

he's an idiot. What do you expect

Magentic aircraft carriers!

 

[hist78]

He verbally said Intel 7 margins were single digit with the new wafer pricing model one at least one of three occasions. It was either the investor meeting where they went over the model for the then upcoming finical break out of the manufacturing group, the meeting going over the recast financials, or the first earnings call after the recast financials. You can find the old transcripts for the presentations and the slide decks at intc.com. But the specific bit about intel 7 specifically being single digit was verbal rather than on a slide (as opposed to other comments about the average margin across across all pre-EUV nodes).

I remember at multiple occasions Intel executives stated that Intel 7 is not cost competitive. For example, Pat Gelsinger mentioned it during his Computex Taipei trip in June 2024 in an interview by a Taiwanese media.

"Q: Intel's foundry business has suffered huge losses over the years. What’s the future for the company’s foundry business?

A: Today, our wafers are largely driven by Intel 10 and Intel 7. Those technologies are not that competitive in terms of processes nor costs. But as we get to the five nodes and four years to Intel 3 and Intel 18A, these are very competitive and much more cost-effective. So, as those technologies ramp up, we will go to break even and then be in a very comfortable profitable business later in this decade. We feel very comfortable with the profitability strategy plan that we've laid out."

https://english.cw.com.tw/article/article.action?id=3709

 

[MKWVentures]

"No customers"? That hasn't been reported yet. But the splitting of Intel has gotten much news this weekend for sure.

Intel BOD has now seen the truth and is doing what is needed. I don't know what the end result will be since it depends on the numbers in the agreements. but all of the options are good for Intel products group.

 

[MKWVentures]

So isn’t the solution to this something like - hey apple , meta , tesla. Have your chips created in the US or else. - D. Trump. All jokes aside - there is a lot of noise out there and I think it is just that. Intel needs a new CEO to stop this bleeding going on with the board. If this new CEO is any good - he will see the immense value in the foundry capabilities built over the last 3-4 years.Intel may very well be in the right place right time finally, with all this politics going on. Frankly Intel splitting would be a travesty business decision IMO. Most recent product launches have been good and new hands in the design pot will secure Intel some demand. Also: amazing users in this forum

I think that ship has sailed unless all the details fall through on the proposals..... How could a CEO take over?

On the "force them to use Intel". I dont think punishing successful US tech companies is a good way to subsidize. This isnt 1995 anymore..... Intel and the US is not the same.

The Spinoffs and JV options are very good for the US and for Intel. They were good options back in 2020 as well.

 

[Artificer60]

The Spinoffs and JV options are very good for the US and for Intel. They were good options back in 2020 as well.

I vehemently disagree. A JV that gives controlling interest to a non-US company spells the end of any US hope for logic technology leadership and makes the US beholden to others for anything on the cutting edge. I fail to see how that is "good for the US". Like it or not, Intel Foundry is America's only hope to remain at the leading edge of logic technology.

 

[MKWVentures]

I vehemently disagree. A JV that gives controlling interest to a non-US company spells the end of any US hope for logic technology leadership and makes the US beholden to others for anything on the cutting edge. I fail to see how that is "good for the US". Like it or not, Intel Foundry is America's only hope to remain at the leading edge of logic technology.

We want foundries in the US. If Intel cannot be successful, then we need successful foundry companies to be in the US. Or if you want, the government can take them over and have "Amfab". I am good either way

Who the controlling interest is will be up for debate in the agreements. I have seen contracts where the country can nationalize the whole thing if certain agreements are not met.

Intel's leading logic technology manufacturing Fab is in Ireland and owned by a JV based in the Cayman Islands. Is this good for Ireland or the US or Cayman islands or all? I am not sure myself.

 

[tedc]

We want foundries in the US. If Intel cannot be successful, then we need successful foundry companies to be in the US. Or if you want, the government can take them over and have "Amfab". I am good either way

Who the controlling interest is will be up for debate in the agreements. I have seen contracts where the country can nationalize the whole thing if certain agreements are not met.

I think folks are still wrestling with what's ideal vs. what's practical. Ideally, you want a US-owned and US-based leading edge, profitable IDM.

Practically, as long as leading edge fabs are being constructed and operated in the US, who owns what, what is a JV, etc. are tactical questions. Know we're nostalgic for the Intel of days past, but almost seems like we want to have our cake and eat it too.

 

[Daniel Nenni]

TSMC could certainly take over the Intel Ohio fabs since they are not built yet. TSMC taking over Intel OR and AZ would be very painful and expensive. It would be better to farm those out to Globalfoundries since they are very experienced in putting fabs out to pasture. Same with Intel Israel and Ireland, That is why they call themselves GlobalFoundries.

Remember, Abu Dhabi still owns controlling interest in GlobalFoundries. Trump already does business with Abu Dhabi and could do a biggly deal there, no problem.

 

[Mooredaddy]

TSMC could certainly take over the Intel Ohio fabs since they are not built yet. TSMC taking over Intel OR and AZ would be very painful and expensive. It would be better to farm those out to Globalfoundries since they are very experienced in putting fabs out to pasture. Same with Intel Israel and Ireland, That is why they call themselves GlobalFoundries.

Remember, Abu Dhabi still owns controlling interest in GlobalFoundries. Trump already does business with Abu Dhabi and could do a biggly deal there, no problem.

Exactly. It would destroy tsmc margins to absorb Intel fabs. There is no reason for them to do it. Better to take trumps ridiculous tarrifs then that

 

[MKWVentures]

TSMC could certainly take over the Intel Ohio fabs since they are not built yet. TSMC taking over Intel OR and AZ would be very painful and expensive. It would be better to farm those out to Globalfoundries since they are very experienced in putting fabs out to pasture. Same with Intel Israel and Ireland, That is why they call themselves GlobalFoundries.

Remember, Abu Dhabi still owns controlling interest in GlobalFoundries. Trump already does business with Abu Dhabi and could do a biggly deal there, no problem.

This is great example of how the options all have trade offs. individual fabs sell off is risky and doesn't generate much return. The whole IFS (TD and All) with a wafer purchase agreement is the cleanest but requires Tons of accounting tricks. And if you really want to sell it off, you cannot get picky with who buys it.... or you need to subsidize it. All things are possible but there are tradeoffs. To sell off a unit with billions in losses, the need for 20B in capex per year, tons of depreciation on the books, and a questionable goal (#2 foundry) is tough. They need a world class accounting team.

Kioxia did some complex financing and control when it was spun off. If only Intel knew someone who had experience with that LOL.