Intel 18A "too good" but design lags

[MKWVentures]

According to Intel's slide, the cost of 18A is on par with tsmc
View attachment 2501

I think we all agree that the Intel powerpoint slides show great success. the ones in 2021 were amazing. Real world cost depends on volume and efficiency in HVM fabs which we will find out about in 2025/2026. First is process technology, then volume, then efficiency at volume. Sounds like the first one is on track. Lets see what next year brings.

 

[IanD]

I think we all agree that the Intel powerpoint slides show great success. the ones in 2021 were amazing. Real world cost depends on volume and efficiency in HVM fabs which we will find out about in 2025/2026. First is process technology, then volume, then efficiency at volume. Sounds like the first one is on track. Lets see what next year brings.

I agree that the Intel slides look good...

Whether this actually means their process is "better" or "worse" for PPA than TSMC in reality (as opposed to Powerpoint-world) very much depends on the assumptions and test cases that were used to generate those slides, as I tried to explain earlier... ;-)

Production cost/yield is a different matter entirely, and I would be astounded if Intel can compete with TSMC here...

 

[nghanayem]

I'm not sure what you mean by "partial BSPDN" on A16 -- AFAIK it's at least technically comparable to 18A and possibly ahead, though the devil is in the details.

Whether 18A has a clock speed advantage and N2 a power/area one will very much depend on which libraries (and whose!) are used for the comparison, since nanosheet transistor physics are going to be similar for both.

I've looked at the N2 libraries and there are a vast number ranging from a small/low drive "mobile" one through a taller "HPC" one, with each also having various different configurations including double-row cells. I'd be very surprised if somewhere in there aren't libraries similar to the 18A ones -- but Intel traditionally targets maximum speed for benchmarks and TSMC traditionally target low power/high density, so it's difficult to know whether PPA comparisons were apples-to-apples.

(and I've also seen figures from a big external IP supplier -- who probably invest more in library development than TSMC does, as I expect Intel does -- showing that their N2 libraries have up to 10% better PPA than TSMC's own).

There's also the added complication that 18A uses BSPD and TSMC have delayed this until A16, but again the advantages of BSPD are heavily reliant on the use case, with significant PPA improvements where there is a dense power grid but not in many devices where there isn't (I've seen the N2/A16 benchmarks) -- as a CPU specialist I would expect Intel to have benchmarked 18A using this case because it makes their process look good...

Yeah, I can add some color to my statement. TSMC said SPR is optional on A16 and that N2 IPs are drop in compatible. This indicates that A16 uses standard cells with the same size as N2, and that the M0/M2 power rails are still there (hence preventing any compaction of the cell height). It is for this reason why I call it a partial implementation as opposed to 18A which is BSPDN only and so it gets all the benefits rather than just a good chunk of them. My observation that A16 doesn't have shrunken cells from N2 is further backed up by their statement of 7-10% density boost, which is exactly inline with intel's findings of a 10% utilization uplift for a Crestmont E core. Of course, as you indicated, the exact benefit will depend on your power grid. A hypothetical chip with practically no PDN would obviously get little to no benefit.

But when you look at things from the perspective of individual transistors is where the larger PPA upside is. As you said, SPR is technologically more advanced than PowerVIA gen 1. SPR won't intrude on the amount of space you have for wider nanosheets, the resistance should be lower, as should the parasitic capacitance. The major impediment native to A16's implementation is not being able to delete the power rails due to the need to support FSPDN and be backwards compatible with N2. Not making A16 BSPDN only provide a cell compaction for every transistor that is not dependent on the exact chip and how routing limited the design is. There is nothing wrong with TSMC doing it this way, and for their business it is almost assuredly the best way to go about things. But it does hurt their area scaling and cost per FET. But you don't need to take IMEC or my words on the matter, let's look at some real examples to illustrate my point:

N5 short NAND cell: 210nm with a 28nm M0 pitch and 7.5 M0 tracks
N3 short NAND cell: 162nm with a 23nm M0 pitch and 7 M0 tracks (2 1.5x M0 tracks for power)
i3 short NAND cell: 210nm with a 30nm M0 pitch and 7 M0 tracks (2 1.5x M0 tracks for power)
i4+20A BEOL cell: 210nm with a 36nm M0 pitch and 5.8 M0 tracks

On i4+powerVIA intel can hit the same cell heights as N5's HD cells even after walking back M0 pitch from the intel 4 30nm to an intel 7 like 36nm. When you compare to N5, N5 needed a 22.2% feature shrink (not far from the 30% needed for a 2x lithographic shrink) to have the same cell height as intel 4 + power via. Allowing for 2D direct print EUV instead of 1D EUV-assisted quad patterning. Intel claims the cost saving was great enough to make the BSP process cost neutral. Put another way, when you use BSP like this you can reset your BEOL lithographic requirements by a full lithographic node of scaling. But you don't need to use it that way either. If you wanted, you could also keep M0 pitch the same and get to smaller cell heights. With the same 5.8 tracks and 30p you could have 174nm height, and with 23p you could do 133nm. Given the slowing of pitch scaling and the cost associated with doing so, I can't overstate how large of a boon this is for the AC part of PPAC. IMEC, intel, and cadence both claim that a BSP only process will shrink cell heights by 20% and AMAT claims a 20-30% cell height reduction. Note: this is NOT the 10% or so utilization increase reported by TSMC and intel for A16/i4+powerVIA. That "up to 10% utilization improvement" is extra gravy on top of the flat 20% area reduction from removing the power rails from the cell (or you can of course can also be used to relax metal pitches and reset metal pitch scaling by a full lithographic node of scaling).

Supporting diagrams and illustrations below courtesy of Cadence, IMEC, and AMAT:

 

[Daniel Nenni]

Not maturity, performance and area.

I should add that customers run tests and simulations using the PDKs on their own designs so the PPA is unique and may not support the marketing slides that the companies put out. In fact, "may not" means will not, not even close, completely different universe, etc.....

 

[IanD]

Yeah, I can add some color to my statement. TSMC said SPR is optional on A16 and that N2 IPs are drop in compatible. This indicates that A16 uses standard cells with the same size as N2, and that the M0/M2 power rails are still there (hence preventing any compaction of the cell height). It is for this reason why I call it a partial implementation as opposed to 18A which is BSPDN only and so it gets all the benefits rather than just a good chunk of them. My observation that A16 doesn't have shrunken cells from N2 is further backed up by their statement of 7-10% density boost, which is exactly inline with intel's findings of a 10% utilization uplift for a Crestmont E core. Of course, as you indicated, the exact benefit will depend on your power grid. A hypothetical chip with practically no PDN would obviously get little to no benefit.

But when you look at things from the perspective of individual transistors is where the larger PPA upside is. As you said, SPR is technologically more advanced than PowerVIA gen 1. SPR won't intrude on the amount of space you have for wider nanosheets, the resistance should be lower, as should the parasitic capacitance. The major impediment native to A16's implementation is not being able to delete the power rails due to the need to support FSPDN and be backwards compatible with N2. Not making A16 BSPDN only provide a cell compaction for every transistor that is not dependent on the exact chip and how routing limited the design is. There is nothing wrong with TSMC doing it this way, and for their business it is almost assuredly the best way to go about things. But it does hurt their area scaling and cost per FET. But you don't need to take IMEC or my words on the matter, let's look at some real examples to illustrate my point:

N5 short NAND cell: 210nm with a 28nm M0 pitch and 7.5 M0 tracks
N3 short NAND cell: 162nm with a 23nm M0 pitch and 7 M0 tracks (2 1.5x M0 tracks for power)
i3 short NAND cell: 210nm with a 30nm M0 pitch and 7 M0 tracks (2 1.5x M0 tracks for power)
i4+20A BEOL cell: 210nm with a 36nm M0 pitch and 5.8 M0 tracks

On i4+powerVIA intel can hit the same cell heights as N5's HD cells even after walking back M0 pitch from the intel 4 30nm to an intel 7 like 36nm. When you compare to N5, N5 needed a 22.2% feature shrink (not far from the 30% needed for a 2x lithographic shrink) to have the same cell height as intel 4 + power via. Allowing for 2D direct print EUV instead of 1D EUV-assisted quad patterning. Intel claims the cost saving was great enough to make the BSP process cost neutral. Put another way, when you use BSP like this you can reset your BEOL lithographic requirements by a full lithographic node of scaling. But you don't need to use it that way either. If you wanted, you could also keep M0 pitch the same and get to smaller cell heights. With the same 5.8 tracks and 30p you could have 174nm height, and with 23p you could do 133nm. Given the slowing of pitch scaling and the cost associated with doing so, I can't overstate how large of a boon this is for the AC part of PPAC. IMEC, intel, and cadence both claim that a BSP only process will shrink cell heights by 20% and AMAT claims a 20-30% cell height reduction. Note: this is NOT the 10% or so utilization increase reported by TSMC and intel for A16/i4+powerVIA. That "up to 10% utilization improvement" is extra gravy on top of the flat 20% area reduction from removing the power rails from the cell (or you can of course can also be used to relax metal pitches and reset metal pitch scaling by a full lithographic node of scaling).

Supporting diagrams and illustrations below courtesy of Cadence, IMEC, and AMAT:
View attachment 2503View attachment 2504
View attachment 2506
View attachment 2505

Thanks for the clarification. I can see why Intel "BSPD-only" has an area advantage over TSMC "BSPD compatible with FSPD", but doesn't that also make an assumption about how the BSPD contacts are made -- I thought that Intel's were offset from the transistors which means they need some extra area, where TSMCs come up directly underneath, have your area estimates allowed for this?

As you say, TSMC have a very strong commercial drive to make cell libraries compatible between FSPD N2 and BSPD A16 -- IP in the sense of higher-level macros is only compatible if it's relaid out with the new PDN, so "high-level" IP like SERDES macros (which have a huge development effort/time) won't be compatible. There are other reasons for staying with FSPD such as lower cost and much less of a hot-spot problem, which is why TSMC only recommend A16 for "actively cooled HPC devices" -- meaning, where the heatsink/cooling plate can be kept cold enough (e.g. no more than 60C). This is a massive downside which excludes BSPD for many applications, including ours... :-(

(I've simulated worst-case hot-spot temperature rises increasing from +20C with N2 (FSPD) to +50C with BSPD, which means the die has to be kept 30C cooler to keep within EM and reliability limits...)

That means Intel may be excluded from a lot of applications if they are BSPD-only, and may force TSMC to continue to support both FSPD and BSPD well beyond N2/A16. That's not a big process cost/support issue since all the difficult/expensive/fine-pitch bits (FEOL/MEOL/BEOL up to top metal layers) are the same, only the thick metal layers and TSVs are different -- but this could prevent TSMC from going "BSPD-only", unless they also fork the IP/libraries into BSPD-only and FSPD variants which is a *lot* of effort -- not just for TSMC but also all the 3rd party IP suppliers, including the digital library suppliers than many customers (including us) use.

My guess is that they'll do this at some point (A14? Axx?), when there's a big enough demand for BSPD and the IP optimized for it -- but will continue to support FSPD for applications that can't switch, which I expect is a large number... ;-)

 

[siliconbruh999]

That's some very nice explanation thanks

 

[Xebec]

Hopefully modern Intel marketing is more accurate:

 

[nghanayem]

Thanks for the clarification. I can see why Intel "BSPD-only" has an area advantage over TSMC "BSPD compatible with FSPD", but doesn't that also make an assumption about how the BSPD contacts are made -- I thought that Intel's were offset from the transistors which means they need some extra area, where TSMCs come up directly underneath, have your area estimates allowed for this?

Yes and no.

So the diagrams intel has shown show the powervia coming up inside the cell boundary region and then the TCNs extending over the top of the boundary region to land on the powerVIA. Since this is below the metal routing layers it does not minimize the benefits I had mentioned about deleting the power rails. However, as you can see from the image what does happen is the nano-TSV reduces the space available for the nanosheets. So all else being equal the nanosheets for a nano-TSV or BPR type of BSPDN cannot be as wide as a BS-TCN/direct epi contact from the BS type of BSPDN process. As I previously mentioned that nano-TSV is a big chunk of extra capacitance, and that a BS-TCN will be shorter/have lower contact resistance than a BPR or nano-TSV scheme. For these reasons it is not shocking that intel was showing off TEMs and E-test data of powerVIA gen 2 BS-TCNs and also BS-GCTs at last year's IEDM both on a regular GAA process and to demonstrate functional CFET inverters. Direct backside contacts are the ultimate end state for BSPDNs and backside signaling. With that said once we are talking CFET the top device will need a BPR/nano-TSV like structure to get their backside connectivity.

As you say, TSMC have a very strong commercial drive to make cell libraries compatible between FSPD N2 and BSPD A16 -- IP in the sense of higher-level macros is only compatible if it's relaid out with the new PDN, so "high-level" IP like SERDES macros (which have a huge development effort/time) won't be compatible. There are other reasons for staying with FSPD such as lower cost and much less of a hot-spot problem, which is why TSMC only recommend A16 for "actively cooled HPC devices" -- meaning, where the heatsink/cooling plate can be kept cold enough (e.g. no more than 60C). This is a massive downside which excludes BSPD for many applications, including ours... :-(

(I've simulated worst-case hot-spot temperature rises increasing from +20C with N2 (FSPD) to +50C with BSPD, which means the die has to be kept 30C cooler to keep within EM and reliability limits...)

That means Intel may be excluded from a lot of applications if they are BSPD-only, and may force TSMC to continue to support both FSPD and BSPD well beyond N2/A16. That's not a big process cost/support issue since all the difficult/expensive/fine-pitch bits (FEOL/MEOL/BEOL up to top metal layers) are the same, only the thick metal layers and TSVs are different -- but this could prevent TSMC from going "BSPD-only", unless they also fork the IP/libraries into BSPD-only and FSPD variants which is a *lot* of effort -- not just for TSMC but also all the 3rd party IP suppliers, including the digital library suppliers than many customers (including us) use.

I think TSMC's BSPDN design enablement ecosystem is just less mature than intel's. Granted, this is to be expected since intel 4+powerVIA was ready to go in 2023 and 18A is launching products about 2 years before A16. I suspect that in time, TSMC's ecosystem will also figure it out. Being able to see 18A product teardowns won't exactly hurt either . Given, intel has demonstrated an 8 E-core CPU (higher thermal density than the P cores) implemented with 95% peak std cell utilization with probe temperatures in line with base intel 4 data running at 3 GHz and 1.1V. Sure, I'm sure the data it's dressed up, but even when you dress up data you can't get results that good without there being some secret sauce at work. What I can say definitively is that intel products will not accept not being able to run at low temps like 60C. CCG wants their 1.6+ volts and 90C operation. So if intel is using 18A for CPUs from datacenter chips at ultra low voltage with hundreds of cores and fancy liquid cooling, to low power laptop chips turboing up to high Vs with no active cooling, then they must have figured it out reasonably well. After all, new device architectures at high yield are Intel's specialty.

My guess is that they'll do this at some point (A14? Axx?), when there's a big enough demand for BSPD and the IP optimized for it -- but will continue to support FSPD for applications that can't switch, which I expect is a large number... ;-)

Agreed, I have to assume A14 will be BSPDN only if they don't want intel running away with a large multi-year process lead. But if TSMC's mobile clientele are squares and demand a front side PDN version of A14, then I have to imagine that A10 at the absolute latest will be BSPDN only. There is just no way to avoid eventually biting that bullet sooner or later, because I have to imagine doing a non design compatible BSPDN only version of A14 alongside a non design compatible FS only A14 would be prohibitively expensive. If nothing else, CFET is impossible without BSPDN/BS-signaling (that is unless TSMC is ok having their CFET process being a sub 10% density uplift).

 

[MKWVentures]

Hopefully modern Intel marketing is more accurate:

View attachment 2510

Many of these chips were made at a factory where I worked. A lot of Intel employees even referred to it as "ITANIC"... HP and Intel combined on this winner of product line.

 

[Daniel Nenni]

Yes and no.
View attachment 2508View attachment 2507


So the diagrams intel has shown show the powervia coming up inside the cell boundary region and then the TCNs extending over the top of the boundary region to land on the powerVIA. Since this is below the metal routing layers it does not minimize the benefits I had mentioned about deleting the power rails. However, as you can see from the image what does happen is the nano-TSV reduces the space available for the nanosheets. So all else being equal the nanosheets for a nano-TSV or BPR type of BSPDN cannot be as wide as a BS-TCN/direct epi contact from the BS type of BSPDN process. As I previously mentioned that nano-TSV is a big chunk of extra capacitance, and that a BS-TCN will be shorter/have lower contact resistance than a BPR or nano-TSV scheme. For these reasons it is not shocking that intel was showing off TEMs and E-test data of powerVIA gen 2 BS-TCNs and also BS-GCTs at last year's IEDM both on a regular GAA process and to demonstrate functional CFET inverters. Direct backside contacts are the ultimate end state for BSPDNs and backside signaling. With that said once we are talking CFET the top device will need a BPR/nano-TSV like structure to get their backside connectivity.
View attachment 2509

I think TSMC's BSPDN design enablement ecosystem is just less mature than intel's. Granted, this is to be expected since intel 4+powerVIA was ready to go in 2023 and 18A is launching products about 2 years before A16. I suspect that in time, TSMC's ecosystem will also figure it out. Being able to see 18A product teardowns won't exactly hurt either . Given, intel has demonstrated an 8 E-core CPU (higher thermal density than the P cores) implemented with 95% peak std cell utilization with probe temperatures in line with base intel 4 data running at 3 GHz and 1.1V. Sure, I'm sure the data it's dressed up, but even when you dress up data you can't get results that good without there being some secret sauce at work. What I can say definitively is that intel products will not accept not being able to run at low temps like 60C. CCG wants their 1.6+ volts and 90C operation. So if intel is using 18A for CPUs from datacenter chips at ultra low voltage with hundreds of cores and fancy liquid cooling, to low power laptop chips turboing up to high Vs with no active cooling, then they must have figured it out reasonably well. After all, new device architectures at high yield are Intel's specialty.

Agreed, I have to assume A14 will be BSPDN only if they don't want intel running away with a large multi-year process lead. But if TSMC's mobile clientele are squares and demand a front side PDN version of A14, then I have to imagine that A10 at the absolute latest will be BSPDN only. There is just no way to avoid eventually biting that bullet sooner or later, because I have to imagine doing a non design compatible BSPDN only version of A14 alongside a non design compatible FS only A14 would be prohibitively expensive. If nothing else, CFET is impossible without BSPDN/BS-signaling (that is unless TSMC is ok having their CFET process being a sub 10% density uplift).

In regards to BSPD, TSMC has the advantage/disadvantage of being customer driven. You can bet that the first implementation will be low risk then additional capabilities will come with the follow-on processes. TSMC's inner circle (Apple, QCOM, AMD, NVDA) will certainly have their say in it, absolutely.

Looking at TSMC packaging, CoWos was all about Xilinx before the rest of the customers jumped on board. That is how TSMC works, customer driven. They literally ask customers what they want then TSMC tells customers what the costs/risks are, it is a collaboration. Apple started this by writing some really big checks but now it is an important part of TSMC's culture.

 

[blueone]

Many of these chips were made at a factory where I worked. A lot of Intel employees even referred to it as "ITANIC"... HP and Intel combined on this winner of product line.

HP did the digital design on the CPU. Intel designed the chipset, which was a multi-CPU-socket design. Intel fabricated both, of course. The whole idea was to get HP off PA-RISC, and letting them design the CPU was apparently the bait. I was involved with the first generation chipset. The Itanium name, derived from the conjunction IT-anium, was coined by Craig Barrett's wife, Barbara. (She was a former US ambassador to Finland, and the Secretary of the US Air Force. A very impressive person.) Unfortunately, Itanium was a derivation of VLIW CPU architecture (called EPIC), which can be useful for special purpose processors (Intel's Gaudi AI chip is said to use VLIW), but for the general purpose case, superscalar architecture is a better parallelism strategy due to the complexity of the VLIW compilation problem. An incredible waste of money and many engineers.

 

[IanD]

Yes and no.
View attachment 2508View attachment 2507


So the diagrams intel has shown show the powervia coming up inside the cell boundary region and then the TCNs extending over the top of the boundary region to land on the powerVIA. Since this is below the metal routing layers it does not minimize the benefits I had mentioned about deleting the power rails. However, as you can see from the image what does happen is the nano-TSV reduces the space available for the nanosheets. So all else being equal the nanosheets for a nano-TSV or BPR type of BSPDN cannot be as wide as a BS-TCN/direct epi contact from the BS type of BSPDN process. As I previously mentioned that nano-TSV is a big chunk of extra capacitance, and that a BS-TCN will be shorter/have lower contact resistance than a BPR or nano-TSV scheme. For these reasons it is not shocking that intel was showing off TEMs and E-test data of powerVIA gen 2 BS-TCNs and also BS-GCTs at last year's IEDM both on a regular GAA process and to demonstrate functional CFET inverters. Direct backside contacts are the ultimate end state for BSPDNs and backside signaling. With that said once we are talking CFET the top device will need a BPR/nano-TSV like structure to get their backside connectivity.
View attachment 2509

I think TSMC's BSPDN design enablement ecosystem is just less mature than intel's. Granted, this is to be expected since intel 4+powerVIA was ready to go in 2023 and 18A is launching products about 2 years before A16. I suspect that in time, TSMC's ecosystem will also figure it out. Being able to see 18A product teardowns won't exactly hurt either . Given, intel has demonstrated an 8 E-core CPU (higher thermal density than the P cores) implemented with 95% peak std cell utilization with probe temperatures in line with base intel 4 data running at 3 GHz and 1.1V. Sure, I'm sure the data it's dressed up, but even when you dress up data you can't get results that good without there being some secret sauce at work. What I can say definitively is that intel products will not accept not being able to run at low temps like 60C. CCG wants their 1.6+ volts and 90C operation. So if intel is using 18A for CPUs from datacenter chips at ultra low voltage with hundreds of cores and fancy liquid cooling, to low power laptop chips turboing up to high Vs with no active cooling, then they must have figured it out reasonably well. After all, new device architectures at high yield are Intel's specialty.

Agreed, I have to assume A14 will be BSPDN only if they don't want intel running away with a large multi-year process lead. But if TSMC's mobile clientele are squares and demand a front side PDN version of A14, then I have to imagine that A10 at the absolute latest will be BSPDN only. There is just no way to avoid eventually biting that bullet sooner or later, because I have to imagine doing a non design compatible BSPDN only version of A14 alongside a non design compatible FS only A14 would be prohibitively expensive. If nothing else, CFET is impossible without BSPDN/BS-signaling (that is unless TSMC is ok having their CFET process being a sub 10% density uplift).

I didn't say the hot-spot numbers I gave (+30C hotter) applied to all devices, they were an extreme case for local hotspots in small circuits with very high power density (can be up to 100W/mm2) not standard digital -- for example, inside the circuits used for 224Gbps SERDES which are clocked at tens of GHz. Nothing to do with "figuring it out", it's basic physics -- the heat conduction from the transistors up through the thin metal layers buried in oxide (ultra-low k dielectrics are even worse) is far poorer then through a silicon substrate, metal via pillars help a bit but they're small and only cover a fraction of the circuit area.

Making assumptions is dangerous, without looking at the actual cases involved in detail -- for sure there will be increasing pressure to go to all-BSPDN as processes shrink further, but unless the thermal problems can be solved this will remain as a significant disadvantage for some products -- and one which gets worse with each node because power densities in W/mm2 are increasing even at the same clock rate, and go up even faster if clock rates increase. But for many products where this isn't an issue the increased density of BSPDN will drive their adoption, once everyone is convinced of the benefits and has seen that it can be reliably and cheaply manufactured.

This isn't just handwaving doom-mongering, I'm directly involved in the design of circuits like this where local hotspots are a really big problem, and BSPDN makes them a whole lot worse... :-(

 

[BruceA]

Many of these chips were made at a factory where I worked. A lot of Intel employees even referred to it as "ITANIC"... HP and Intel combined on this winner of product line.

Which fab was that ?

 

[OneEng]

According to Intel's slide, the cost of 18A is on par with tsmc
View attachment 2501

Intel's mouth straight to God's ear

I fail to see how Intel's cost per wafer (fully loaded) on 18A can possibly be less than TSMC's cost on N2 for the following reasons:

1) N2 does not have BSPD and likely takes fewer passes than 18A
2) N2 cost will be spread over a ton of chips from many companies while 18A will be for Intel only in 2025 (for the most part) and will be used by others slowly in the following years .... all while Intel continues to pay for the equipment AND bring their new NXE 5000 series EUV scanners on line for 16A.

I think that Intel is making a mistake messing around with the numbers so their processor divisions look decent and the foundry looks very bad. You can't "hide the weeny" forever .

 

[OneEng]

I agree that the Intel slides look good...

Whether this actually means their process is "better" or "worse" for PPA than TSMC in reality (as opposed to Powerpoint-world) very much depends on the assumptions and test cases that were used to generate those slides, as I tried to explain earlier... ;-)

Production cost/yield is a different matter entirely, and I would be astounded if Intel can compete with TSMC here...

... and even a bigger question, can Intel make a profit doing it?

Everyone seems focused on the technical details (not unusual in a forum filled with Engineers ), but the real fight for Intel is in how long they can afford to remain unprofitable. Seems to me like they have missed the boat strategically as even IF 18A is a wonder node for them, the proceeds and profit of that success will still need 2 or more years to show up. I am not sure they have that long.

 

[Maximus]

... and even a bigger question, can Intel make a profit doing it?

This is a problem I also constantly think about.

Regarding the product side, I don't think the margins for server, desktop, and laptop CPUs will return to previous levels, even if Intel regains process leadership. AMD has become a significant competitor in both performance and volume.

On the foundry side, TSMC holds over 60% of the market share and 90% of the operating profit share. It's unlikely that Intel can capture a substantial market share and maintain profitability simultaneously, even if they manage to overcome the numerous challenges in providing foundry services.

The only segment with the volume and margins Intel needs is the AI GPU market. However, Intel is currently third in this area, and there's no clear path for them to close the gap with AMD and Nvidia.

We haven't even touched on the hidden costs (or less profit) associated with 'Smart Capital' and 'IDM 2.0'.

 

[Fred Chen]

Intel 18A has two sets of interconnects (backside and frontside) which have to be separately aligned and patterned. TSMC A16 would be the same.

Intel Details PowerVia Chipmaking Tech: Backside Power Performing Well, On Schedule For 2024

www.anandtech.com

 

[nghanayem]

Intel 18A has two sets of interconnects (backside and frontside) which have to be separately aligned and patterned. TSMC A16 would be the same.

View attachment 2523

Intel Details PowerVia Chipmaking Tech: Backside Power Performing Well, On Schedule For 2024

www.anandtech.com

Maybe I didn't understand what you meant, but wasn't that always a given regardless of implementation? Similar to making the statement that a transistor's contacts need to be aligned to the transistor and not shorting to the wrong terminal or the wrong transistor.

 

[IanD]

Intel 18A has two sets of interconnects (backside and frontside) which have to be separately aligned and patterned. TSMC A16 would be the same.

View attachment 2523

Intel Details PowerVia Chipmaking Tech: Backside Power Performing Well, On Schedule For 2024

www.anandtech.com

I thought that with A16 the TSVs came up directly underneath the transistors (bottom-side contact) instead of up into a "NanoTSV" and then sideways into the transistor like Intel?

Same alignment problem (top-side vs. backside) but in theory more efficient/advanced -- though this advantage (more than?) disappears if TSMC then use the same libraries with power rails as N2...

(which they don't have to, but have chosen to for the time being -- presumably to speed up TTM and reduce IP costs and allow easier porting from N2 to A16)

 

[OneEng]

I thought that with A16 the TSVs came up directly underneath the transistors (bottom-side contact) instead of up into a "NanoTSV" and then sideways into the transistor like Intel?

Same alignment problem (top-side vs. backside) but in theory more efficient/advanced -- though this advantage (more than?) disappears if TSMC then use the same libraries with power rails as N2...

(which they don't have to, but have chosen to for the time being -- presumably to speed up TTM and reduce IP costs and allow easier porting from N2 to A16)

Based on reading (and re-reading) the contents of this thread and the outstanding information being discussed, I can completely see why TSMC would take the less technically aggressive, and more business flexible solution over Intel's 18A direction.

The effort in moving designs from one node to the next is a really big deal for foundry customers. The ability to service a wide spectrum of different customer designs is also a key metric that a foundry-as-a-service company needs to be very cognitive of.

I am now wondering about the business viability of the less flexible 18A process vs TSMC's N2, then A16, then A14 approach? All of these processes (including 18A) are more expensive than big military equipment (and we are talking about full submarines here. Pretty much everything but an aircraft carrier!). I would hate to get something like this wrong.