MKWVentures
Moderator
As I mentioned before, His comments are becoming increasingly erratic. And the consequences are getting larger as more people are looking at them.
just look at the finances and what the CFO says.
Intel shares jump despite massive loss as chipmaker touts ‘solid progress’ cutting costs
- Thread starter XYang2023
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just look at the finances and what the CFO says.
^ this is your answer for how intel keeps intel 3 around for the long haul. i4 is basically just i3-early and 20A was basically just 18A-early to steal terminology from Samsung, or the equivalent of N5 (Apple and Huawei before they got sanctioned only) vs N5P (what everyone inclusive of Apple and Huawei would use a year after the initial ramp with TSMC's select early customers) in TSMC terminology. They also claimed in early 2023 that they got a billion dollar plus datacenter/edge client on intel 3 (or more likely in current terminology intel 3-E or PT). Either way, external foundry or not; base dies, chipsets, and storage controllers are respectable wafer volume parts with long contract lifecycles. Disaggregation might also make it so intel 3 is "relevant" for a longer period of time.
- Intel 4 is still using SAQP. Do we know, if this is also true for i3?
- i3 seems to be quite ok process (judging by Xeons), so why are there no external customers? Are tools and PDK not ready? Is there not enough capacity? Too expensive?
Intel 3 is supposed to be a foundry node, so if there was a customer, Pat would be all over it.
- i3 seems to be quite ok process (judging by Xeons), so why are there no external customers? Are tools and PDK not ready? Is there not enough capacity? Too expensive?
Intel 3 is supposed to be a foundry node, so if there was a customer, Pat would be all over it.
I guess it is because the features are not ready for external demand. They intend to make intel 3 a long lasting node though, planning to offer several variants on Intel 3, Intel 3T, 3E, 3PT, etc.
Yes Intel says they use SAPQ for those nodes. At VLSI intel said the main application of EUV in the BEOL was for greatly simplifying blocks/cuts, via patterning, and the medium pitch metal layers. 30nm M0 is also too tight to comfortably do EUV direct print. So Intel would either need to do EUV SAPD from a 60nm backbone or SALELE (something Intel hasn't ever done before). For their 28nm and below metal layers TSMC does EUV SALELE. For theirs I think Samsung does SALELE too, but from my memory of the images of 4LPE M0 I have seen I dont recall seeing the tell tale signs of SALELE.
Keep in mind the timeframe of foundry engagements and chip design. Intel claims RPL took 3.5 years to go from PowerPoint to launch and how this is the fastest CCG has ever gone from design to launch. RPL was just ADL with some mobile power saving improvements, more cache, and using the latest Intel 7 process revision. Just imagine how long the design cycle is for non derivative programs like say snapdragon X elite or Nvidia Blackwell. When Intel announced they were doing a foundry push the fabless ecosystem and customers would have already been working on enabling work with TSMC on N2, N3 contracts had long since been signed with red ink, and N5 products were in HVM/qualification. For perspective TSMC claims that they developed processes in around 5 years during the old days and that now it takes them 7 years to develop a process. So even if Intel 3 and to a lesser extent 18A had always been intended as a foundry nodes and had huge ecosystems building from the day Intel started process definition TSMC was always going to win the lion's share of 5, 3, and 2nm contracts because people had hitched their wagons to TSMC before foundry was even a thing.
There is also the unknown quantity angle. Who in their right mind would hitch their wagon to Intel 3 after Intel just finished negotiating massive contracts with TSMC in a pivot to a fab/investment-lite business model. At least with Samsung you know what you are getting.
I think the best Intel can do on Intel 3 (from the external end of things anyhow) is work to sell their high performance 5nm class node with 3nm class HP logic/analog density to a small subset of customers with similar goals or needs to Intel's internal needs (base dies and chipsets) and then port/tweak whatever those customers need (assuming the ROI makes sense). Which seems to be exactly what 3-PT is. By the time Intel starts moving chipsets and base dies to like 18A and or 14A in the 2030s or whatever, hope that enough of an ecosystem has developed around 3 that Fab34/44 can be filled predominantly on external business. Worst case scenario you partially convert Ireland to 18A. Not ideal but not too bad.
He did, look at their old earnings calls. You can't just talk about it all the time. Same with the customer who put down an 18A prepay. Investors don't care about what you did. They care about what have you done for me lately; and that means what new customers did you sign. They also are looking for any and all 18A news as that is supposed to be Intel's overhauling TSMC moment (at least from a process technology and HPC power performance perspective).
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MKWVentures
Moderator
As the CFO has stated multiple times... and I have stated. 18A will NOT be in high volume at the end of 2025. That is not even planned. In this context, high volume is defined by me to be >25K wafers per month of Production (more than half a fab). 18A is a 2026-2027 impactor. It will add a lot of costs but not much revenue in 2025 per the CFO
It will be ramping up some but the Intel products will be in low volume and the external products are just sampling. If Panther Lake and Clearwater forest are LAUNCHED in 1H 2025, this could change. The Plan today is that they both launch in 2H 2025
You are absolutely right. In its earnings call, Pat G actually used word "head to head" compeition instead of "leadership" to describe 18A's position.
Just curious - did Meteor Lake ever hit 25K wafers per month?
hist78
Well-known member
Yes, a company can change the depreciation schedule mid-way through an asset's life, as long as the CPA/auditors approve it. Another consideration is the impact on taxes. Accounting calculations based on GAAP/IFRS may not align with those used by tax authorities, and they are allowed to be different.
In general, a longer depreciation schedule could increase a company’s tax liabilities due to reduced expenses. But in Intel's case, taxes aren’t the primary concern because the company is expecting large losses for the coming years. Intel’s Q3 2024 earnings report clearly shows that Intel is recording all kinds of charges and losses now to prepare for the future, such as tax liabilities and tax credits. Right now, Intel's biggest concerns are cash flow and shrinking revenue—not potential tax obligations.
Additionally, the CHIPS Act tax credit scheme may significantly reduce Intel’s taxes, if any.
Sounds smart, right? Not really.
Consider this: if Intel and TSMC each bought the same model of EUV machine and began using it simultaneously in Arizona. After five years of depreciation, TSMC would have almost no remaining machine cost or small cost to consider in pricing its services. But five years in, Intel would still have three more years of depreciation for the same EUV machine in its cost structure. This would put Intel at a disadvantage in terms of pricing competitiveness. But as long as Intel’s financials look better today, who cares about five years from now?
Five years later, most of the top Intel executives making decisions today will probably have happily retired by then.
Just pop-up a question: if we use the same definition as PG did, from 2021-2024, how many nodes tsmc delivered in 4 years? Will it be 9N4Y? or just N3/N4/N6 3 nodes?
18A will be competing with N2P and N2X, not just the vanilla N2 SoC version. Interesting times.
MKWVentures
Moderator
nope... it never hit high volume (the math is easy BTW)... thats why Pat stated the margins are down and Intel4 costs way over forecast on the Q2 Call.
Intel needs huge foundry and all chips internal to break even and survive. but they had to give up on 20A as it wasnt cost effective to ramp it based on volume.
Let see if Intel can get a fabs worth of foundry customers by end of 2026 ....
By TSMC's metric of at least a 2% PPA improvement counting as a node, TSMC has done 6N4Y (N5P, N4, N4P, N3B, N3E, N3P) during the same period of intel's 5N4Y. By Intel's metric of anything with a greater than 10% PPA improvement counting as a node, TSMC has done 3N4Y (N5 -> N4P, N4P -> N3B, and N3B -> N3P).
By the patent pending Nghanayem metric of "any process with major process flow changes counts as a node" I would call it 2N4Y for TSMC (N3B and N3E with it's completely reworked FEOL process) and 2N4Y (intel 4 and 18A) for intel. If you feel like a PPA amount should also be attached to it, a 1.3-1.5x PPA improvement seems reasonable as the minimum bar to clear. 1.3x PPA is what TSMC touts for N2, and it would feel weird to call anything less "a full process node" even in this day and age. With that said, I don't even know how you could make major process flow changes just to get say a 10% PPA improvement, unless your deliberate goal was to waste money and make changes that didn't even do anything. So I doubt that 1.3-1.5x PPA clause will need to be used very often to call if a process is a full node or not. The only examples that come to mind is when Samsung swapped out their 32/28nm process from a gate first to a RMG process, when TSMC moved their 32/28nm to RMG and canceled their poly Si version because it would have been terrible, and the previously mentioned FEOL rework of N3B to make N3E and sidestep their issues with SAC and self-aligned-gate-endcaps.
I never quite got why Intel do not use their own 7nm process for the I/O die instead of outsourcing it to TSMC. That is lame as heck. Are the economics of Intel 7 that bad? Other than the Foveros base tiles what other uses for DUV will continue moving forward with new products?
Intel shares jump despite massive loss as chipmaker touts ‘solid progress’ cutting costs
Intel's Gordon Moore Park campus at Ronler Acres in Hillsboro.Mike Rogoway/The Oregonian Intel’s stock price was up 9% in late trading Thursday after the company reported third-quarter sales at the high end of its forecast range and touted progress in cutting jobs and expenses. Embattled CEO...
semiwiki.com
Yes, intel said the GM on intel 7 wafers sold at fair market prices was single digit.
Only passive foveros dies don't use EUV, active base die foveros is on intel 3-T/PT. Other than passive foveros there are EMIB dies, the odd new Altera Agilex FPGA, and that is about all I can think of for brand new currently unreleased products on DUV nodes. Intel products doesn't really have a use for old processes nodes other than for chipset standalone/co-packaged dies. Unlike Samsung's design arm who does analog/power stuff, RF, CMOS image sensors, etc. so they (Samsung) have many uses for old logic process nodes.
Intel 7 is used for the base die for Granite Rapids and Sierra Forrest. Also the upcoming Clearwater Forrest will have IO tile on Intel 7.
Artificer60
Well-known member
The development factory in D1 should be ramping and running volume on 18A before the Arizona fab begins to ramp to support the Panther Lake and Clearwater Forest launches. It will probably only be in the 8-10K wafers per month, but that is still revenue. I guess it depends on what you call meaningful. But I think everything Intel does to plug the gaping hole in the bottom of the Foundry bucket counts.