Personally I think people will skip N2 and wait for N2+. Same thing happened for 20nm, N10, and N7+, right? When there are new design/IP considerations the majority of the herd are a bit more cautious when approaching the waterhole. Long live N3x!
Apple's new iPhone chip has us worried about TSMC's 3nm silicon and next-gen GPUs
- Thread starter tonyget
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Personally I think people will skip N2 and wait for N2+. Same thing happened for 20nm, N10, and N7+, right? When there are new design/IP considerations the majority of the herd are a bit more cautious when approaching the waterhole. Long live N3x!
I guess it depends on how much AI they push to the edge. Automotive is probably the best example. Much more CPU performance is needed for autonomous cars but the batteries are much bigger than the iPhone 15 so die size is not as much of an issue.
I think there is an argument that innovation is faster today then the times of yore. TSMC 65nm was 30-50% PPW. 40nm was 40% PPW and 50% Power @iso Perf. 28nm was 20% and 40% respectively. On a 2-3 year cadence from 65>40nm>28 this gives ~17% PPW uplift per year. N3E>N2 is ~7% annual improvement. Objectively this is a slowdown. However I think there is a rarely talked about variable. Cycle time and process complexity. Talking from a generic level if it only takes a week for TSMC to get a data turn on how a process change did, then you can improve yields and performance faster then if it takes 2 weeks to get that data turn. For the development of N2 TSMC needed to pack more innovation while having slower data turns than those older nodes. I think there is a strong argument that from the process side delivering 41% the improvements in the same amount of time (from the perspective of the fabless firms that use the stuff) means that the rate of innovation is faster when the rate of learning is lower.
I think the more "concerning" part is the PPW. Despite the only minor rise in transistor count and small xPU performance uplifts, the N3 SOC has the same battery life as the prior N4P one. Wireless and analog design are FAR from my expertise, but based on the specs it doesn't seem like there should be any major uptick in power from those components either. But I did put ""s around concerning for a reason. I don't think this should be surprising to folks. TSMC's own marketing says N3's efficiency characteristics are a sidegrade vs N4P.
There's also the issue with N2/N2+ that this transition is *not* like previous half-nodes (e.g. N7/N6, N5/N4, N3E/N3P) where all the IP is reusable -- the PPA attraction of N2+ is BPD, but this needs a complete relayout and recharacterisation of all IP, new libraries (standard cell/RAM) and custom IP such as SERDES, and rejigging the tools to separate out front-side and back-side interconnect. It's the biggest design/tool change for many years -- N2 is the last of the "frontside power" processes, N2+ is the first of the "backside-power" processes which is then likely to become the new standard. Compared to this, switching from planar to FinFET was simple...
I think anyone using N2 is unlikely to switch to N2+ due to the limited benefit, they're more likely to wait for N1.5 (or whatever the next process is called) to get a big step forward to justify the big redesign cost/effort. I agree that anyone on N3 is unlikely to switch to (dead-end) N2, if they're going to redesign they might as well go the whole hog and wait for N2+ which then gives them a clear path forwards as well as a further PPA improvement.
This is always the problem with a node where there's a step change in technology...
I'm waiting to see when backside power is available. That might be the swing vote to get people going on N2. Apple will be first, hopefully for the iPhone 2025 products but probably 2026. We will get an update next week at TSMC OIP. Exciting times in the ecosystem, absolutely.
According to Apple’s A17 Pro scores in Geekbench 6’s single-core test, it scored within 10% of AMD's Ryzen 9 7950X and Intel's Core i9-13900K processors. The A17 Pro scored 2,914 points in single-core testing, while the Core i9-13900K scored 3,223 and the Ryzen 9 7950X scored 3,172. Though these are impressive results, it’s important to note that Apple's A17 Pro operates at 3.75 GHz while the Core i9-13900K and Ryzen 9 7950X operate at a much higher 6.0GHz and 5.8GHz, respectively.
I doubt most iPhone users will feel the difference in the A16 or A17 or even the A15. My wife has an iPhone 12, I have a 14 Pro, no difference in user experience for what we do.
I doubt most iPhone users will feel the difference in the A16 or A17 or even the A15. My wife has an iPhone 12, I have a 14 Pro, no difference in user experience for what we do.
From current status of N2 development, it's unlikely to catch 2025 iPhone. My guess is tsmc will hold a N2 mass production ceremony in the end of 2025 like they did for N3B in Dec 2022, so tsmc can claim N2 mass production in 2025.
Hence my guess on iPhone SOC is
2023 A17 N3B --> 2024 A18 N3E --> 2025 A19 N3P --> 2026 A20 N2 --> 2027 A21 N2P (with backside power)
Agreed. The majority of the other customers will probably stay with N3 until N2P, skipping N2. Just my opinion of course, it depends on the ecosystem and the design considerations.