Apple’s A17 and M3 yield is only 55%
- Thread starter chillfire
- Start date
Says who? I have it on authority that it is 80%+
According to the link below. Source is EE Times
wccftech.com
A17 Bionic, M3 Yields At TSMC’s 3nm Process Are Sitting At 55 Percent, Apple Said To Pay For The Known Good Dies Rather Standard Wafer Prices
TSMC is said to switch to normal wafer pricing with Apple next year, as the company’s A17 Bionic and M3 yields sit at 55 percent
According to the link below. Source is EE Times
A17 Bionic, M3 Yields At TSMC’s 3nm Process Are Sitting At 55 Percent, Apple Said To Pay For The Known Good Dies Rather Standard Wafer Prices
TSMC is said to switch to normal wafer pricing with Apple next year, as the company’s A17 Bionic and M3 yields sit at 55 percent
And I’m telling you that is a complete fabrication based on rumors and opinions of outsider analysts and journalists. Apple has never and will never buy good die from TSMC.
But they fooled you so that is something.
Mooredaddy
Well-known member
Ohhhh get em Dan. My man in no mood for BS today lol
The sad thing is that EETimes used to be the gold standard. It used to come in the mail every Monday and I couldn't wait to read it. My first published article was in EETimes in the 1990s and we framed it. Now it is all about the clicks and there is so much noise you have to be outrageous to be heard. Sad times in the semiconductor industry, absolutely.
Mooredaddy
Well-known member
I went and read the article and it was just quoting what analysts are projecting and guessing yields are atm. Truly terrible journalism. Because we know how accurate analysts are. And of course it gets reposted and amplified by other tech websites with less sophisticated views of the semi industry. Truly shameful.
I read Ian Cutress but you need to remember that he has zero semiconductor industry experience. He does however have an admirable education. I wish he was working in the semiconductor industry rather than commenting on it. https://www.linkedin.com/in/iancutress/
I saw Ian at SEMICON West / DAC last week. One of the few analysts that actually shows up. Nice guy too.
I sat with some of the traditional press you mentioned in SEMICON West briefings. Embarrassing. Made me feel young and smart which is rare.
Yield is a difficult topic. For one thing it is highly protected by NDAs. Another is that it is a moving target so you may be right today but wrong tomorrow.
Apple and TSMC jointly develop the processes. TSMC N3 was delayed. There is no way yield was at 50% when production started and there is no way Apple paid for good die. Apple owns the yield as much as TSMC does.
Samsung has been known to ship good die when it has serious yield problems. We are talking single digit yields. Since Samsung Foundry is a tiny part of Samsung semiconductor it can be hidden. TSMC does not have that luxury. Bad yield will be known.
Hi Dan, I'm curious to understand how Apple or other fabless players can help drive yield at foundry. Is it through design changes or does fabless have proprietary process methodology?
Design collaboration. With Apple that design collaboration starts very early since the process is developed jointly with TSMC. Apple also does iterative designs so it is much easier to do. It really is a unique relationship between Apple and TSMC, not unlike an IDM with inhouse design. It really did disrupt semiconductor manufacturing, absolutely.
hist78
Well-known member
This Wccftech article, published on July 13, is based on another article published by EETimes on April 25, 2023. This Wccftech author decided to write an article using a more than 2.5 month old information/rumor (may not even true) is very strange.
tooLongInEDA
Moderator
To be fair to wccftech, the article's headline is straplined "Mobile : Rumor" ! Though it's written with far more certainty than it merits. I guess it's a combination of gossip column and cut and paste press release/other article journalism. Doing the actual background research and checks takes time. And thought.
As an illustration of the design collab which Dan mentions, consider if test and metrology identifies some feature within the chip which is repeatedly failing. They will dive into the cause - litho interference on tight features, layer alignment too loose, etching margins, signal drive too slow, voltage sag too much, thermal, etc. - and then figure out how to avoid it. This will often result in tweaking the EDA rules to improve them, possibly cleaning up some other places where the same problem occurred but less obviously. In other cases the foundry will agree they can improve the machinery, tweak a metal thickness, get tighter control of exposure threshold, etc. These are in the broad class of DFM (design for manufacturability) and a pilot customer like Apple would be aware of the burden they are signing up for.
You will find a lot of DFM papers at recent semi conferences. Making an advanced process yield is not simply machinery, it is also keeping your design within guard rails and having accurate EDA for safe layout, timing, power, and other verification. On a run of thousands of wafers the measurement and metrology may generate repeated corrections.
Thank you so much for the additional context
Great example, thank you. This is why Apple get's a unique version of the first TSMC process. Changes can be made for Apple that others may not benefit from. That is the benefit of being loyal to TSMC not to mention being responsible for 25% of TSMC's revenue.
Investor call:
CC Wei:
Now let me talk about our N3 and N3E status. Our 3-nanometer technology is the most advanced semiconductor technology in both PPA and transistor technology. N3 is already involved in production with good yield. We are seeing robust demand for N3 and we expect a strong ramp of N3 in the second half of this year, supported by both HPC and smartphone applications.
N3 is expected to continue to contribute mid-single-digit percentage of our total wafer revenue in 2023. N3E further extend our N3 family with enhanced performance, power and yield and provide complete platform support for both HPC and smartphone applications. N3E has passed the qualification and achieved performance and yield target and will start volume production in the fourth quarter of this year.
CC Wei:
Now let me talk about our N3 and N3E status. Our 3-nanometer technology is the most advanced semiconductor technology in both PPA and transistor technology. N3 is already involved in production with good yield. We are seeing robust demand for N3 and we expect a strong ramp of N3 in the second half of this year, supported by both HPC and smartphone applications.
N3 is expected to continue to contribute mid-single-digit percentage of our total wafer revenue in 2023. N3E further extend our N3 family with enhanced performance, power and yield and provide complete platform support for both HPC and smartphone applications. N3E has passed the qualification and achieved performance and yield target and will start volume production in the fourth quarter of this year.