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TSM builds capacity on orders only, Others should take note

Arthur Hanson

Well-known member
TSM is well known for only building capacity on orders with deposits, others should proceed with caution if they don't. TSM though has one large advantage, they are at the bleeding edge in semi production and there is no other option. Other companies can only wish they had this position. Will any company come out with a process ahead of TSM? That is the big question.
 
TSM is well known for only building capacity on orders with deposits, others should proceed with caution if they don't. TSM though has one large advantage, they are at the bleeding edge in semi production and there is no other option. Other companies can only wish they had this position. Will any company come out with a process ahead of TSM? That is the big question.
Agreed.... we will see what happens when actual wafer starts don't materialize for these companies planning lots of Foundry Fabs. To choose a competitor over TSMC, they would have to have a better technology (unlikely), Lower price (maybe), Better reputation for delivering (unlikely), better scale (impossible). Lets see how that works out
 
It sure doesn't make sense for Samsung, but it makes every sense for Intel as they are the leading-edge foundry and a major chip design company.

TSMC is struggling to meet Apple's demand. And so it makes sense for Intel to build these many fabs in order to reserve capacity for both future internal and external demands.

Samsung isn't the leading chip design company, they failed miserably with their Exynos mobile SoCs. So they can only count on external demands and wish that the demand is strong.

Unlike Samsung, Intel is a true IDM. They have a huge internal demand as well as external demand. With these many capacity coming online in the future. Intel will be able to

1. Move AI/GPU chips and many others to be manufactured in house.
2. Find more external customers to fill the fab.
3. Compete more aggressively on Pricing against AMD and NVIDIA because they are making the profit margin of AMD and slightly less margin of TSMC.
 
TSMC is struggling to meet Apple's demand. And so it makes sense for Intel to build these many fabs in order to reserve capacity for both future internal and external demands.
Unlike Samsung, Intel is a true IDM. They have a huge internal demand as well as external demand. With these many capacity coming online in the future. Intel will be able to

1. What signs indicate that tsmc is "struggling" to meet Apple's demand? And if so, why Apple see Intel as the 2nd option but not Samsung?
2. Where are "huge external demands" to Intel? For future, there might be some external demands but now you cannot see them from IFS's revenue.
 
TSMC is struggling to meet Apple's demand. And so it makes sense for Intel to build these many fabs in order to reserve capacity for both future internal and external demands.

Absolutely not true. Apple pays for fabs optimized for Apple products. The only time TSMC "struggles" to meet Apple's demand is when Apple overshoots their forecast. Even then TSMC can jack up utilization and be the hero. Worst case Apple repeats a process if TSMC cannot deliver a new process within the Apple product delivery window, which has happened.
 
1. What signs indicate that tsmc is "struggling" to meet Apple's demand? And if so, why Apple see Intel as the 2nd option but not Samsung?
2. Where are "huge external demands" to Intel? For future, there might be some external demands but now you cannot see them from IFS's revenue.
1. you can refer to https://www.eetimes.com/tsmcs-3-nm-push-faces-tool-struggles/, yeah, they will eventually reach a healthy yield, as they did many times in history. And here's the thing, Apple may never see Intel as second option nor Samsung because TSMC is already building 3nm fabs in Arizona. In case anything happens, they will have capacity to go through the winter.
2. and where do you see me mention of "huge external demand", I said "huge internal demand and external demand". I never anticipated they will have the same external demand as TSMC, but a nice external demand if they manage to execute on 18A.
Absolutely not true. Apple pays for fabs optimized for Apple products. The only time TSMC "struggles" to meet Apple's demand is when Apple overshoots their forecast. Even then TSMC can jack up utilization and be the hero. Worst case Apple repeats a process if TSMC cannot deliver a new process within the Apple product delivery window, which has happened.
same article as I mentioned above,
"
Apple will pay TSMC for known good die rather than standard wafer prices, at least for the first three to four quarters of the N3 ramp as yields climb to around 70%, Brett Simpson, senior analyst at Arete Research, said in a report provided to EE Times.

“We think TSMC will move to normal wafer-based pricing on N3 with Apple during the first half of 2024, at around $16-17K average selling prices,” Simpson said. “At present, we believe N3 yields at TSMC for A17 and M3 processors are at around 55% [a healthy level at this stage in N3 development], and TSMC looks on schedule to boost yields by around 5+ points each quarter.”
"

Look, I never consider Foundry are at a winning position yet if they can't get yield good enough. If they charge customers for good die rather than standard wafer price because of poor yield. They are struggling. They may be able to get to a good yield rate or they may not be able to. Who knows? They may be late or may be early with their goals. Who knows? But if they haven't achieved a healthy yield, I won't call TSMC/s N3 as done. Just like Samsung's process nodes that are not done because they didn't get to a healthy yield as TSMC. Will you consider Samsung's 3nm as not struggling on their roadmap when they just start ramping their first customer?
 
1. you can refer to https://www.eetimes.com/tsmcs-3-nm-push-faces-tool-struggles/, yeah, they will eventually reach a healthy yield, as they did many times in history. And here's the thing, Apple may never see Intel as second option nor Samsung because TSMC is already building 3nm fabs in Arizona. In case anything happens, they will have capacity to go through the winter.

That article is based on speculation.

"Taiwan Semiconductor Manufacturing Co. (TSMC) is straining to meet demand from top customer Apple for 3-nm chips. The company’s tool and yield struggles have impeded the ramp to volume production with world-leading technology, according to analysts surveyed by EE Times."

How about surveying people who actually work inside the semiconductor ecosystem?

Of course TSMC says N3 will be fully utilized, but again, TSMC builds fabs for Apple which are not shared with other customers. The Apple N3 process is optimized for Apple devices so anybody who says Apple will take capacity from other customers or other customers take capacity away from Apple are misinformed.

As for the other N3 customers, since TSMC N3 is the dominant 3nm for foundry customers of course there will be tight supply the first year in production but it will not be tight for Apple.

Check the wording on these analyst quotes: We think, we believe, we expect... These are called opinions not facts.

Bottom line: The Apple/TSMC relationship is quite unique and like no other I have seen in my 30+ years of foundry experience (experience not speculation). TSMC and Apple jointly develop a process and freeze it when all parameters are at an acceptable level. Since Apple does iterative designs rather than brand new designs it is not as difficult, however, Apple pushes the boundaries of design and process technology which is why TSMC is now the undisputed leader ahead of semiconductor giants Intel and Samsung.
 
That article is based on speculation.

"Taiwan Semiconductor Manufacturing Co. (TSMC) is straining to meet demand from top customer Apple for 3-nm chips. The company’s tool and yield struggles have impeded the ramp to volume production with world-leading technology, according to analysts surveyed by EE Times."

How about surveying people who actually work inside the semiconductor ecosystem?

Of course TSMC says N3 will be fully utilized, but again, TSMC builds fabs for Apple which are not shared with other customers. The Apple N3 process is optimized for Apple devices so anybody who says Apple will take capacity from other customers or other customers take capacity away from Apple are misinformed.

As for the other N3 customers, since TSMC N3 is the dominant 3nm for foundry customers of course there will be tight supply the first year in production but it will not be tight for Apple.

Check the wording on these analyst quotes: We think, we believe, we expect... These are called opinions not facts.

Bottom line: The Apple/TSMC relationship is quite unique and like no other I have seen in my 30+ years of foundry experience (experience not speculation). TSMC and Apple jointly develop a process and freeze it when all parameters are at an acceptable level. Since Apple does iterative designs rather than brand new designs it is not as difficult, however, Apple pushes the boundaries of design and process technology which is why TSMC is now the undisputed leader ahead of semiconductor giants Intel and Samsung.

Sure, you can be right. It may not be a capacity or tooling issues. I can be misguided.

But my earliest post remains valid. The world needs a better 2nd place foundry. Intel has the ability to do so. And they should do it regardless of external demand because they have huge internal demands that require them to get to better process technology as early as possible.
 
But my earliest post remains valid. The world needs a better 2nd place foundry. Intel has the ability to do so. And they should do it regardless of external demand because they have huge internal demands that require them to get to better process technology as early as possible.

Agreed. If you look at the history of Intel and AMD there is a clear case for competition to drive semiconductor innovation. TSMC needs this competition as well. Everybody runs faster in a race.. I'm not talking about a press release or media race, I'm talking about customers in high volume production.

The media and analysts can bash TSMC all they want but the PDKs are what customers look at and PDKs don't lie. Today TSMC has the only production 3nm PDK and there is no arguing that, the 3nm race is over. 2nm will be a new competition and I hope we do have (3) PDKs to choose from. But I have to warn you, 2nm is a new technology. It took time for us to perfect FinFETs and it will take time for us to perfect nanosheets, absolutely.
 
Sure, you can be right. It may not be a capacity or tooling issues. I can be misguided.

But my earliest post remains valid. The world needs a better 2nd place foundry. Intel has the ability to do so. And they should do it regardless of external demand because they have huge internal demands that require them to get to better process technology as early as possible.
Let see what Intel delivers. Right now, Intel has plenty of Fab capacity for internal products. They are using TSMC for some because TSMC has better options than Intel. Lets see if Intel leads in technology, delivery and scale..... If they cut price to win, it will be a billion dollar nightmare. And Intel internal demands may be lower, not higher. We will see. Just to reiterate: Intel fabs are underloaded today. AND Intel is choosing to use TSMC for many chips. These are facts. Lets see if it changes .... in a positive or negative for Intel.
 
Let see what Intel delivers. Right now, Intel has plenty of Fab capacity for internal products. They are using TSMC for some because TSMC has better options than Intel. Lets see if Intel leads in technology, delivery and scale..... If they cut price to win, it will be a billion dollar nightmare. And Intel internal demands may be lower, not higher. We will see. Just to reiterate: Intel fabs are underloaded today. AND Intel is choosing to use TSMC for many chips. These are facts. Lets see if it changes .... in a positive or negative for Intel.
Except the decision as to where to make parts was made many moons ago, when Intel fabs were not underloaded, and before they had clarity as to how well their future nodes would do.

So, decisions on current products (or close to) don't indicate the status of current fabrication technology. Using TSMC was the only logical choice at the time they did, for things that didn't prioritize performance above all else.

Having said all that, I have concerns about the performance of their "4" process. It might be like 10nm where the initial clock speeds aren't great (although obviously not as painfully bad as 10nm was initially), and will get better, but I think they will just move past it since they have other nodes available soon. But, if Intel 4 had really good clock speeds, why would Raptor Lake Refresh be their leading desktop parts? And that's not a long ago decision.

My bet, Intel 7 will continue to be the best performance node, and Intel will obviously hit new clock speeds with the refresh, whereas Intel 4 will likely never hit those clock speeds, and even with the IPC advantages, Meteor Lake will not perform at the same level. But, mobile is 80% of the market, and clearly it will be better in density and power efficiency at laptop power scenarios, so that's more important I guess.
 
1689392323895.png
 
I'm not sure exactly how to read this. Is it saying Intel 3 and Samsung's 3 are going to be a lot more dense than TSMC's 3? Like they will be .5 of the size? Or it is a chart where higher is better, and it's really saying they will be twice the size. I'm thinking the latter, because it appears it's normalized on one bar (this being the TSMC 2nm on the left side), and if 3nm and 2nm are related, it's difficult to see all three becoming less dense as they move to that. Again, assuming that's how the chart is made.

Also, how much do we trust the people making this? Is TechInsights a source you have a good degree of confidence in?
 
I'm not sure exactly how to read this. Is it saying Intel 3 and Samsung's 3 are going to be a lot more dense than TSMC's 3? Like they will be .5 of the size? Or it is a chart where higher is better, and it's really saying they will be twice the size. I'm thinking the latter, because it appears it's normalized on one bar (this being the TSMC 2nm on the left side), and if 3nm and 2nm are related, it's difficult to see all three becoming less dense as they move to that. Again, assuming that's how the chart is made.

Also, how much do we trust the people making this? Is TechInsights a source you have a good degree of confidence in?

Very trusted. This is from Scott Jones, I saw him at SEMICON West. It shows that TSMC has the most dense process and Intel the best performance. The value is normalized, 1 being the best then down from there. Not surprising based on what I have heard inside the ecosystem. If IFS can get the 18A PDK in good form they can get some high performance chiplet business, absolutely. Cost is another thing entirely, I’m working on that, but cost may be less of a concern with chiplets.
 
Very trusted. This is from Scott Jones, I saw him at SEMICON West. It shows that TSMC has the most dense process and Intel the best performance. The value is normalized, 1 being the best Then down from there. Not surprising based on what I have heard inside the ecosystem. If IFS can get the 18A PDK in good form they can get some high performance chiplet business, absolutely. Cost is another thing entirely, I’m working on that, but cost may be less of a concern with chiplets.
You can easily see from those charts why customers are looking more at 18A at Intel than Intel 3. It's a little surprising to me Intel again sold out so much for performance, which would make sense for their internal CPUs, but not much sense as a foundry. Who really needs that extra performance delta, outside of Intel, at such a cost in density? And it's not that great of a performance delta over TSMC's 3nm. And given this is a final FinFET node, it could have long term implications.

Now, we all know Intel gets crazy performance improvements in their latest nodes over the initial release, but that isn't the problem that potential customers really need solved, it's the density. And it's not going to improve, if history is a guide, on Intel 3. I'm not sure they made the right choices if it were designed with external customers in mind as well as their internal use. 18A you could make a better argument for. It's a lot faster, and the density isn't nearly as hideous as the "3" comparison. Even so, it's definitely skewed for internal usage, but it's a lot more competitive than "3". As I mentioned, it all ties in, with seemingly limited interest in Intel 3, and more interest in 18A.
 
You can easily see from those charts why customers are looking more at 18A at Intel than Intel 3. It's a little surprising to me Intel again sold out so much for performance, which would make sense for their internal CPUs, but not much sense as a foundry. Who really needs that extra performance delta, outside of Intel, at such a cost in density? And it's not that great of a performance delta over TSMC's 3nm. And given this is a final FinFET node, it could have long term implications.
I would think DC customers, given that power draw is a very large portion of their op cost/TCO. Just to round the plots to easy numbers, let's call 18A as 125% the performance and 75% the density of N2. Hypothetically with N2, you could make a chip with 25% more cores (of course using 25% more power while doing it and potentially running into a harder memory bottleneck). This same design on 18A would either cost more for the same core count or have to have fewer cores for a similarly sized die. For this example let's say they chose to make the same die size. you would then have say 100 cores running fast enough that they match 125 N2 cores, while also using less power due to the lower core count. You could also just take the 25% performance hit and use 40% less power.

On the topic of density, there are some aspects that I would love to see how they impact real chip designs (as opposed to the theoretical density we are talking about). We will have to see how well EDA tools/designs utilize BSPD, but based on the std cell utilization we were seeing at VLSI, powervia might be a non obvious part of the density story. If your N2 design on avg has like 60% utilization while the 18A one has like 80%, then that is probably almost as good as shrinking the cells (as far as the designers are concerned). Of course the cells having smaller blank spaces between them would also increase thermal density. However what I am less sure about is if this would be as big of a hit, or a bigger hit than a pure pitch shrink (all else being equal). Another aspect that I would love to see how it shakes out with real products would be the different nanosheet stacks and how they impact the PPA of analog devices/other less dense logic libraries (after all, even mobile chips are not just short cells and HD SRAM).
Now, we all know Intel gets crazy performance improvements in their latest nodes over the initial release, but that isn't the problem that potential customers really need solved, it's the density. And it's not going to improve, if history is a guide, on Intel 3. I'm not sure they made the right choices if it were designed with external customers in mind as well as their internal use. 18A you could make a better argument for. It's a lot faster, and the density isn't nearly as hideous as the "3" comparison. Even so, it's definitely skewed for internal usage, but it's a lot more competitive than "3". As I mentioned, it all ties in, with seemingly limited interest in Intel 3, and more interest in 18A.
Should this aspect be surprising? Intel announced it's aspirations to jump into foundry after Pat came back. Would it not make sense for nodes that started development before foundry was the goal to be optimized around intel's use cases rather than LP mobile SOCs? If we were to assume that intel's development time for a brand new node was similar to TSMC's 4 years, then 20/18A had to have started work in 2020 while BS was still CEO. As for the intel 3 vs N3E density, yeah that's what delays will do to a new technology.
 
I would think DC customers, given that power draw is a very large portion of their op cost/TCO. Just to round the plots to easy numbers, let's call 18A as 125% the performance and 75% the density of N2. Hypothetically with N2, you could make a chip with 25% more cores (of course using 25% more power while doing it and potentially running into a harder memory bottleneck). This same design on 18A would either cost more for the same core count or have to have fewer cores for a similarly sized die. For this example let's say they chose to make the same die size. you would then have say 100 cores running fast enough that they match 125 N2 cores, while also using less power due to the lower core count. You could also just take the 25% performance hit and use 40% less power.

On the topic of density, there are some aspects that I would love to see how they impact real chip designs (as opposed to the theoretical density we are talking about). We will have to see how well EDA tools/designs utilize BSPD, but based on the std cell utilization we were seeing at VLSI, powervia might be a non obvious part of the density story. If your N2 design on avg has like 60% utilization while the 18A one has like 80%, then that is probably almost as good as shrinking the cells (as far as the designers are concerned). Of course the cells having smaller blank spaces between them would also increase thermal density. However what I am less sure about is if this would be as big of a hit, or a bigger hit than a pure pitch shrink (all else being equal). Another aspect that I would love to see how it shakes out with real products would be the different nanosheet stacks and how they impact the PPA of analog devices/other less dense logic libraries (after all, even mobile chips are not just short cells and HD SRAM).

Should this aspect be surprising? Intel announced it's aspirations to jump into foundry after Pat came back. Would it not make sense for nodes that started development before foundry was the goal to be optimized around intel's use cases rather than LP mobile SOCs? If we were to assume that intel's development time for a brand new node was similar to TSMC's 4 years, then 20/18A had to have started work in 2020 while BS was still CEO. As for the intel 3 vs N3E density, yeah that's what delays will do to a new technology.
My background is likely different from most people's here, but more cores is not always better. Single-threaded performance always is, although to varying degrees. If you need more cores to get the same performance, in the absolutely best case scenario, then you have an inferior processor. Because my cores will always be able to take advantage of their extra performance, whereas you'd need something that somehow could be able to use all the cores to equal the performance, and that's just not common for CPUs. GPUs? Yeah. For CPUs, you run into Amdahl's law.

On top of that, as you get more cores, you run into bottlenecks not only with memory, but also with the bus used. How scalable is a bi-directional ring bus? Mesh bus adds latency. So, for client computing there's no way Intel's approach isn't superior. Now, for servers, it gets a lot closer. For GPUs, depending upon what the real numbers are, and the power efficiency, density definitely is a very important quality.

And we see this playing out already, with Intel's superior clock speeds giving them the edge in client situations, but in servers it's different (except where Intel has specialized instructions and such). And in GPUs? Not even Intel makes their GPUs on their process. Of course, they will close the gap, but the situation is somewhat familiar.

But, I never said one way or another one process was superior. Just that 18A was a lot more desirable, vis-a-vis TSMC's offerings, than their 3nm. Even 18A seems inferior in many contexts, because most companies will not care as much about crazy clock speeds as Intel does. But, at least it's closer, and easier to make a case for. I just don't see many scenarios for 3nm at all.

Naturally, there are other considerations too.

Also, let's not forget, Intel was working on being a foundry before Gelsinger jumped in. He definitely put more energy into it, but he was not the first person who thought of it, and it was part of their plans long before he got there. But, I'm a little surprised on I3, mainly because of the magnitude of the density difference. Given the quick cadence, I thought I4 was going to be a very high performance node for internal use, and I3 more of an external node. Intel was singing this song for a while, but based on these charts, it doesn't appear very attractive even for that.
 
On top of that, as you get more cores, you run into bottlenecks not only with memory, but also with the bus used. How scalable is a bi-directional ring bus? Mesh bus adds latency. So, for client computing there's no way Intel's approach isn't superior. Now, for servers, it gets a lot closer. For GPUs, depending upon what the real numbers are, and the power efficiency, density definitely is a very important quality.

And we see this playing out already, with Intel's superior clock speeds giving them the edge in client situations, but in servers it's different (except where Intel has specialized instructions and such). And in GPUs? Not even Intel makes their GPUs on their process. Of course, they will close the gap, but the situation is somewhat familiar.
Performance =/= clockspeed, and that hasn't been the case since like the late 90s. In the modern context performance has varying definitions. Most often it seems to entail clocks or on-current @x volts, @y leakage, and/or @iso power. It is also worth remembering performance is also not a uniform number either. Back when intel was lapping TSMC on process tech, TSMC's nodes gave competitive performance per watt characteristics at the bottom end of the power envelope.
But, I never said one way or another one process was superior. Just that 18A was a lot more desirable, vis-a-vis TSMC's offerings, than their 3nm. Even 18A seems inferior in many contexts, because most companies will not care as much about crazy clock speeds as Intel does. But, at least it's closer, and easier to make a case for. I just don't see many scenarios for 3nm at all.
I do agree that to the wider foundry market density seems to be more valued than performance, although I suspect there are limits to how far folks would go for density. For example take intel's claims for 10nm vs 14++. 10nm was WAY denser than 14++ (probably pretty close to 3x given the CPP relaxation that happened on 14++). Even if 10nm performed/yielded where intel originally would have wanted it too, it would have still had worse PP characteristics than 14++. This then leads to a dilema, would someone like a Qualcomm then chose to tape out a snapdragon on 14++ or 10nm? IMO, that depends on the product, but if we assume that the Freq/V curve maintained the same pattern even at the bottom of the curve, and that QCOM could get the functionality they wanted at a die cost that was acceptable on 14++; then I think they would have picked 14++ over 10nm. As for DC (the part of the foundry market that has been growing the fastest of the past few years), density is a secondary concern (doubly so now that everyone is moving in the direction of disag). Does it matter how expensive H100 is to produce? At the prices they are being sold for, not really. Does it matter how much power it draws? Absolutely! If for example the tops/W somehow got worse than A100, customers would rather buy more A100s than fewer H100s.
Naturally, there are other considerations too.
Of course. Nothing is ever as simple as a single number when we are talking process technology. Unfortunately these F/V curves and seeing the size of the std cell libs are about as good as we can get for comparing nodes without doing taredowns and spending weeks discussing all of the aspects where node A or B is better in xyz categories.
Also, let's not forget, Intel was working on being a foundry before Gelsinger jumped in. He definitely put more energy into it, but he was not the first person who thought of it, and it was part of their plans long before he got there.
ICF got iced right at the end of BKs tenure. I find it hard to imagine that BS was planning a resurrection while simultaneously telling investors intel will begin outsourcing key products.
But, I'm a little surprised on I3, mainly because of the magnitude of the density difference.
Are you surprised N5 is so much larger than N3 too? The former 7nm was supposed to be launching products back during the infancy of N5. Intel leadership even talked about it as a better than their 5"nm" node. Three years later and intel still claims a 2x boost, but is now competing with a node that is 1.6x the maximum theoretical density.
Given the quick cadence, I thought I4 was going to be a very high performance node for internal use, and I3 more of an external node. Intel was singing this song for a while, but based on these charts, it doesn't appear very attractive even for that.
How is this still not the case. It presumably has all of the features i4 lacked. Unless all nodes have now been obsoleted by N3E, I fail to see how intel 3 is "unsuitable as a foundry node" just because the HD lib is half as dense as N3E (assuming techinsight's projections come to pass). Does that mean I expect intel 3 to take the world by storm? Not in the slightest. But I think that is a TTM problem rather than intel should have made i4/3 more aggressive problem.
 
Performance =/= clockspeed, and that hasn't been the case since like the late 90s. In the modern context performance has varying definitions. Most often it seems to entail clocks or on-current @x volts, @y leakage, and/or @iso power. It is also worth remembering performance is also not a uniform number either. Back when intel was lapping TSMC on process tech, TSMC's nodes gave competitive performance per watt characteristics at the bottom end of the power envelope.

I do agree that to the wider foundry market density seems to be more valued than performance, although I suspect there are limits to how far folks would go for density. For example take intel's claims for 10nm vs 14++. 10nm was WAY denser than 14++ (probably pretty close to 3x given the CPP relaxation that happened on 14++). Even if 10nm performed/yielded where intel originally would have wanted it too, it would have still had worse PP characteristics than 14++. This then leads to a dilema, would someone like a Qualcomm then chose to tape out a snapdragon on 14++ or 10nm? IMO, that depends on the product, but if we assume that the Freq/V curve maintained the same pattern even at the bottom of the curve, and that QCOM could get the functionality they wanted at a die cost that was acceptable on 14++; then I think they would have picked 14++ over 10nm. As for DC (the part of the foundry market that has been growing the fastest of the past few years), density is a secondary concern (doubly so now that everyone is moving in the direction of disag). Does it matter how expensive H100 is to produce? At the prices they are being sold for, not really. Does it matter how much power it draws? Absolutely! If for example the tops/W somehow got worse than A100, customers would rather buy more A100s than fewer H100s.

Of course. Nothing is ever as simple as a single number when we are talking process technology. Unfortunately these F/V curves and seeing the size of the std cell libs are about as good as we can get for comparing nodes without doing taredowns and spending weeks discussing all of the aspects where node A or B is better in xyz categories.

ICF got iced right at the end of BKs tenure. I find it hard to imagine that BS was planning a resurrection while simultaneously telling investors intel will begin outsourcing key products.

Are you surprised N5 is so much larger than N3 too? The former 7nm was supposed to be launching products back during the infancy of N5. Intel leadership even talked about it as a better than their 5"nm" node. Three years later and intel still claims a 2x boost, but is now competing with a node that is 1.6x the maximum theoretical density.

How is this still not the case. It presumably has all of the features i4 lacked. Unless all nodes have now been obsoleted by N3E, I fail to see how intel 3 is "unsuitable as a foundry node" just because the HD lib is half as dense as N3E (assuming techinsight's projections come to pass). Does that mean I expect intel 3 to take the world by storm? Not in the slightest. But I think that is a TTM problem rather than intel should have made i4/3 more aggressive problem.

I'm not sure what you're talking about with performance =/= clock speed. It never has been the case, NEVER. Performance is, and always has been, IPC x clock speed. I'm sure you must already know that, so I'm going to assume you mean clock speeds with with different voltages, which you allude to, which makes sense to me, but makes little sense in the context of that chart. It seems obvious to me the chart is referring to something approximating higher clock speeds. Intel nodes can hit the highest clock speeds, and the power curve is less malicious at top end. You can't get an AMD processor to hit the same clocks as Intel, at any the highest speeds, as the appreciation of clock speed to power use gets catastrophic. Even moreso than Intel's which clearly lose efficiency pretty fast too. They can't overclock as high, and they aren't clocked at the same speed stock. So, if you want to get into something more complicated than the chart implies, you're arguing with the chart. But, clearly it means Intel chips will be able to clock the highest. Will they be able to clock the highest at every voltage, for example, power draw? No, but it's kind of understood by most what the chart is implying. At the higher ranges, Intel chips should clock the highest. At the lowest voltages, I'd expect that not to be true, but that's not what the chart is really talking about. At least I assume it is not.

We don't have power usages, so I didn't even bother talking about them. They aren't within this context because of that. But, looking at a GPU, for example, yes, you do care about how much it costs, always. You saw NVIDIA complaining about it. And here's the gist of it, which you even alluded to without doing it explicitly, if I can pop more transistors in there, and achieve the same performance as something with fewer, but running at higher clock speeds, do I win? In a CPU, nope! In a GPU, almost certainly, because as you mention, performance isn't everywhere the same, neither is power usage. In almost all cases, if I can clock my GPU lower, and get the same performance, I will almost certainly get better efficiency, since efficiency generally gets worse and worse as you go up in clock speed, particularly as you reach for the highest clocks available. And, power use matters a lot.

What is this nonsense about using quotes around something I never said? If you're going to quote me, quote something I said, not something obtusely manufactured and put into your words. I never said I3 was "unsuitable as a foundry node", I don't like absolutes enough to say something so definitive. But, it's clearly less attractive, vis-a-vis the competition than 18A apparently will be. And if you don't believe that, just pay attention to the messaging now. I3 isn't getting much talk or interest, apparently, whereas Intel is now talking much more about 18A. Do you think that's completely unrelated to its relative merits and just timing and other aspects? I don't, I also don't think it's entirely based on what is described in these charts, but it's got something to do with it.

Clearly, I3 does not have all the features I4 lacked, high density being a primary one. It's certainly got many improvements, and also took EUV usage to a much higher level, and hopefully will be less expensive to make, but saying it has all the features I4 lacked is simplistic. Could one say, for example, I3 lacks PowerVIA? Sure can, but then, what defines lacking? It's an idiotic conversation to have. But, what both lack is, competitive density. Power use? I guess we'll have to see what that curve looks like. If it's very good, well, my feeling is that will be very important to a lot of people, if the power use within their context is favorable. So, the verdict isn't in yet, but I find them calling something I3 with such relative poor density a bit misleading. And let's remember, the 3nm, or i7, etc... was a way of expressing size. And surely, I3 doesn't measure up (yeah, I'll slap myself for you, for using such a lousy pun). But, nowadays they are a bit more liberal with their meanings, so I guess it's not as damning as it would have been.
 
I'm not sure what you're talking about with performance =/= clock speed. It never has been the case, NEVER. Performance is, and always has been, IPC x clock speed. I'm sure you must already know that, so I'm going to assume you mean clock speeds with with different voltages, which you allude to, which makes sense to me, but makes little sense in the context of that chart. It seems obvious to me the chart is referring to something approximating higher clock speeds. Intel nodes can hit the highest clock speeds, and the power curve is less malicious at top end. You can't get an AMD processor to hit the same clocks as Intel, at any the highest speeds, as the appreciation of clock speed to power use gets catastrophic. Even moreso than Intel's which clearly lose efficiency pretty fast too. They can't overclock as high, and they aren't clocked at the same speed stock. So, if you want to get into something more complicated than the chart implies, you're arguing with the chart. But, clearly it means Intel chips will be able to clock the highest. Will they be able to clock the highest at every voltage, for example, power draw? No, but it's kind of understood by most what the chart is implying. At the higher ranges, Intel chips should clock the highest. At the lowest voltages, I'd expect that not to be true, but that's not what the chart is really talking about. At least I assume it is not.
For chips that is how you calculate performance. I'm talking from a process perspective. 22nm is listed as 18% more performant than 32nm. For top desktop parts clockspeed of sandy->ivy went up 100MHz. Sky-> kaby single core turo was only a 20% boost rather than the 26% performance from 14++. Did intel lie? No. This is just the post Dennard world we live in where you don't get power and density and clocks for no work. At the low end of the voltage curve where the leakage is manageable you will see performance = clockspeed. But at high voltages not so much.
We don't have power usages, so I didn't even bother talking about them.
Because if at x voltage you clock y% faster you can lower voltage and get the same performance. If iso power is acceptable you can keep voltage the same and get enough performance to potentially make up for a density disadvantage.
They aren't within this context because of that. But, looking at a GPU, for example, yes, you do care about how much it costs, always. You saw NVIDIA complaining about it. And here's the gist of it, which you even alluded to without doing it explicitly, if I can pop more transistors in there, and achieve the same performance as something with fewer, but running at higher clock speeds, do I win? In a CPU, nope! In a GPU, almost certainly, because as you mention, performance isn't everywhere the same, neither is power usage. In almost all cases, if I can clock my GPU lower, and get the same performance, I will almost certainly get better efficiency, since efficiency generally gets worse and worse as you go up in clock speed, particularly as you reach for the highest clocks available. And, power use matters a lot.
This is my whole point. A hypothetical 18A HPC chip should use less power at iso performance to an N2 chip. If you want to use the extra density N2 provides to add more SMs/EUs/CUs, you can do that @iso die are, but you will be adding that to your power budget (even if it is generally more efficient than boosting freq).
What is this nonsense about using quotes around something I never said? If you're going to quote me, quote something I said, not something obtusely manufactured and put into your words. I never said I3 was "unsuitable as a foundry node", I don't like absolutes enough to say something so definitive. But, it's clearly less attractive,
That is my bad, I misunderstood your wording.
I3 isn't getting much talk or interest, apparently, whereas Intel is now talking much more about 18A. Do you think that's completely unrelated to its relative merits and just timing and other aspects? I don't, I also don't think it's entirely based on what is described in these charts, but it's got something to do with it.
Technically 18A is the only IFS node with no locked in customer deal at this point. Presumably if there was we would have heard it during an investor call. Timing has everything to do with a node's competitiveness. If I am a first wave TSMC customer intel 3 has no value to me, because N3E is coming out with close enough PPW and better density. If I am a second wave customer intel 3 is also dead to me because it is only going to start it's deprecation/yield/cost learning curves with the intel 4 ramp (leading to higher wafer pricing than what TSMC will probably offer from their soon to be fully depreciated N5 fabs). If intel 3 came out in 2021 they would be far enough along the listed curves that they could snag more second wave customers, and snag wave 1 customers from the WAY better performance and power characteristics. Density would also not be a problem given HP library is pretty darn close to the N5 HD.
Clearly, I3 does not have all the features I4 lacked, high density being a primary one.
I don't think you understand intel 4/3. For one density is not a feature it is a characteristic. By this notion intel 7 and N5 are not fully featured because they are less dense than N3E (which would also be missing features compared to N2). Two as far as we know, intel 4 only has a HP library and the devices to allow the MTL CPU die to talk with everything else. As far as we can tell from VLSI, intel 4 can make no other products besides MTL and the "custom networking ASIC".
Sure can, but then, what defines lacking?
Having all of the devices to make a fully featured SOC (supporting a radio being optional) is a good start.
It's an idiotic conversation to have. But, what both lack is, competitive density. Power use? I guess we'll have to see what that curve looks like. If it's very good, well, my feeling is that will be very important to a lot of people, if the power use within their context is favorable. So, the verdict isn't in yet, but I find them calling something I3 with such relative poor density a bit misleading. And let's remember, the 3nm, or i7, etc... was a way of expressing size. And surely, I3 doesn't measure up (yeah, I'll slap myself for you, for using such a lousy pun). But, nowadays they are a bit more liberal with their meanings, so I guess it's not as damning as it would have been.
I can see the slightly misleading angle to it. Truth be told if I was CEO for a day when this was made, I would have moved away from any scheme that could be implied to have a nm number or be compared to another firm's. I would have picked giving it some name, just calling it by the Pxxxx number, or use greek letters with numbers denoting nodelets in the series. I'm sure intel's argument would probably be that intel's metric since the day of intel accelerated has ALWAYS been "process performance per watt leadership by 2025". If that is the metric we are measuring, then I suppose you could even call it intel 2. Although I (and many many others) would not take kindly to this name. I suspect the 4/3 names were chosen by the following logic:

"Our HP library has the same density as N5's HD and we have better PPA/PPW than N5-N4P but worse density than N3. Let's call our node intel 4 as it sits kind of between them.".
Someone then asked "What do we call our 18% performance kicker once we enable the rest of the PDK?".
The response was "We don't want to do +s any more given how we ran that into the ground. 18% is also a full node on the PPW front and TSMC has lowered the number by doing less, all right we'll call it intel 3".

As for the nm number I am not going down this rabbit hole. The numbers stopped corresponding to features since like 130nm. Since then they only communicate that things are advancing.
 
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