Litho exposures and etches are often on the scale of minutes. Anneal is also pretty fast. Deposition, CMP, ovens, ALD, and Etches that are either highly selective or highly anisotropic can be much slower. Best publication would be throughput quotes from tool vendors.
This was discussed recently in another thread: https://semiwiki.com/forum/index.ph...phone-15-gpu-price-increase.17097/#post-56510
This.
Yes, that aspect I'm familiar with -- the general cycle time vs throughput curves pop up in some academic literature on fab operations research; as well as "Factory Physics" (Hopp & Spearman)
Any recommendations for which tool vendor(s) might be willing to answer questions of this sort from a random engineering blogger?
Unfortunately my guess would be none. ASML publicly does. Although this is helped by the less layer dependent nature of exposure. Nikon and Cannon might but I wouldn’t know for sure.
It depends on what you make and who your customers are. Foundries need shorter cycle times to respond to changing market conditions. If you are making diodes you might not care about cycle time and just load up the fab. If you are early in the yield curve for memory you also need short cycle time, etc.
Well, it sounds like lithography isn't really the driver of cycle time since it's so short (but is a primary driver of fab capital cost!), so that's less interesting to me... (the only tangible times for some of this stuff I could find so far in published literature was an article in Future Fab in 2001 by someone from ST, with average time for litho of on the order of only 1 minute, but I wasn't sure if that was one pass out of several consecutive passes, or the full lithography time.)
Little is for random queueing. The IEEE Transactions on VLSI Systems have had a number of articles on fab scheduling and optimization. The simplest case is you make one product for a long time. You build a process pipeline and tune it so the most expensive processes run at ideal capacity, other machines may be underutilized. You can approach 100% with little extra delay in those. A DRAM or NAND plant may be close to this.
And what a premium it is -- we recently needed TSMCs ultra-stupid-fast TAT for a 5nm chip, extra cost was $2.5M to get 10 day faster processing... :-(
If you don’t mind me asking how many wafers were you expediting?
so the MTT"F" (mean time to "failure" = adjustment actually) is.... once an hour? day? week? month? year?
Not sure, it was a standard lot so presumably 25 or 50 wafers. I don't think the fee depends on this, it's because it "queue-jumps" -- all the other products in the line literally stop to get out of the way of a lot like this -- so the productivity of the entire line drops. For the same reason there are only a very small number of such slots per line available each month...
Depends on the tool. I hear Ion implanters have low time to fail. And then there is individual tool model as well. Besides the obvious some tool models are better than others, some work better with certain recipes/layers. There are also some dog tools that have problems for multiple PM cycles. On aggregate we have counters that guide PM schedules to avoid the worst of this and minimize the amount of unscheduled downtime.
Those were some seriously expensive wafers.
Yeah, but if you really *really* need to get samples ASAP it's still "only"*** adds <20% to the 5nm mask costs that you're paying for anyway, so <5% to the total chip NRE cost -- and if it makes the difference between meeting and missing a timescale you've promised to a critical customer... ;-)
