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FAKE NEWS: TSMC's 3nm foundry price breaks through $20,000, iPhone 15, GPU price increase

Daniel Nenni

Admin
Staff member
The global wafer foundry 7nm advanced process technology battle is over, not only 7nm EUV has won the first victory, 5/4nm has won AMD, Apple, Broadcom, Intel ( Intel) and others have expanded orders, and NVIDIA and Qualcomm (Qualcomm) have returned their annual masterpieces one after another, and the gap between the two sides continues to widen.

However, according to the semiconductor industry, facing Samsung Electronics’ (Samsung Electronics) 5/4nm and 3nm GAA process yield rate is low, most chip manufacturers have to tighten their cooperation with TSMC, which also makes TSMC’s 3nm process Although the original FinFET is still used, it still easily won large orders from many factories. In addition to Apple and Intel, whose progress has been delayed, Qualcomm, MediaTek, and NVIDIA have also booked production capacity for 2023 and 2024.

TSMC's process technology is advancing generation by generation, and prices continue to hit new highs
TSMC's process technology is advancing generation by generation, and prices continue to hit new highs


However, this dominance situation will also allow the price of each generation of wafer foundries to rise sharply without any resistance. It is understood that 3nm has already exceeded 20,000 US dollars. With the sharp increase in production costs, the chip industry is bound to pass it on to downstream customers and consumers, and the price of new terminal products will no longer go back.

Although Samsung Electronics continues to release news about its cooperation with Qualcomm and other big names, it will also be the first to enter the 3nm GAA generation at the end of June 2022. However, according to semiconductor industry sources, Samsung has been unable to solve the yield problem since the 5nm generation, and the same is true for 4nm. As a result, Qualcomm, which originally placed orders for Samsung, had to turn to TSMC for help in the face of MediaTek's pursuit. After the Snapdragon 8 Gen1 Plus, the latest flagship mobile platform Snapdragon 8 Gen 2 continues to use TSMC 4nm.

Although Qualcomm does not rule out that after entering the GAA process, the flagship masterpiece may restart Samsung and TSMC's bilateral order strategy, but the semiconductor industry believes that the cost of transferring orders is high, and it is very difficult for Samsung to increase the yield rate in the short term and catch up with TSMC. The cooperation will start one and a half years ago, and the initial investment cost is expensive, so the chances of Qualcomm fully switching to Samsung are small, or it is possible to place a symbolic order under the mutually beneficial commercial cooperation with Samsung.

It’s not just that Qualcomm is expanding its orders to TSMC, but it is fully embracing TSMC’s AMD with a process below 7nm. It has been rumored that Samsung is grabbing orders at low prices. Coupled with the consideration of risk diversification, a small number of products are considered to be cast on Samsung’s 5/3nm process. , but the latest platform has appeared, and the next-generation GPU and CPU are still all ordered by TSMC 5nm.

In addition, in addition to NVIDIA’s H100 order for TSMC’s 4nm, the RTX 40 series with the largest order also switched to 4nm. Coupled with the largest customers Apple and MediaTek, TSMC’s 5/4nm capacity utilization rate is still at full capacity. , making up for the 7nm order reduction gap.

According to the semiconductor industry, after entering the 5/4nm process generation, in addition to Samsung itself, almost all chip manufacturers including Intel have also cooperated with TSMC, and have reserved 3nm production capacity, and the N3 process will be mass-produced in the fourth quarter. The quantity is not much, because Intel revised the blueprint, so the main customer is Apple.

By 2023, N3E and other manufacturing processes will be fully scaled up, and there are not many companies that can afford the 3nm manufacturing process. All customers are embracing TSMC. In this situation, except for TSMC’s cautious promotion of advanced manufacturing processes, it will not rashly adopt "bending" In addition to the strategy of "overtaking the road", in fact, Samsung's own setbacks are also the key fuel for TSMC to dominate the advanced manufacturing process.

However, the process technology has been advancing generation by generation, and the price has continued to rise. According to the semiconductor industry, TSMC released a 90nm wafer at the end of 2004, using a 193nm immersion exposure machine with water as the medium to replace the traditional 157nm dry exposure. This machine has rewritten the specifications of exposure machines in the global semiconductor industry, and also broke through the challenge of Moore's Law. At that time, the price of 90nm process wafers was nearly 2,000 US dollars, and that of 65nm process wafers exceeded 2,000 US dollars.

In 2008, the 40nm process increased slightly to around US$2,600. In 2014, the 28nm process exceeded US$3,000. The price of 10nm increased significantly, and each 12-inch wafer came to around US$6,000. So far, 28 Nanometers are sufficient for most products, but process technology must continue to advance in order to cope with high-end to mid-range mobile products, consumer applications, AI, Netcom, 5G, and high-performance computing products such as CPUs and GPUs.

After entering the 7nm generation, the quotation per wafer has doubled to nearly US$10,000, and the price of 5nm has exceeded US$16,000. This does not include another 6% price increase in 2023.

The semiconductor industry said that the high foundry price of 5/4nm, and the quotation of 3nm even reached 20,000 US dollars, which will make the cost of chip manufacturers quite high, which will be passed on to downstream customers. The quotations will be higher than when the old products were launched in the same period.

In fact, the official price of the RTX 4090 launched by NVIDIA in the fourth quarter is 5-10% higher than that of the 3090 graphics card released in the same period of 2020. The market has a lot of doubts about NVIDIA's strategy of going against the trend with full inventory in the upstream and downstream of the supply chain and weak demand.

NVIDIA CEO Jen-Hsun Huang said bluntly that although performance improvements are limited, the increase in new products is reasonable, because the price of 12-inch wafer foundries has risen sharply compared to the past, not just a little more expensive.

It is worth noting that although the price of the iPhone 14 series, which has greatly increased in cost, has not soared, the semiconductor industry expects that the A17 chip that Apple will use in the iPhone 15 series in 2023 will use TSMC's expensive N3E process, and the quotation for each chip will increase significantly. The cost of other components is also rising, and under the pressure of global inflation, the iPhone 15 series is bound to increase, and the increase will be quite impressive.

 
I get the impression that digitimes and trendforce regularly put out articles with rather dubious sourcing. Where is the place to look to find the latest on TSMC and semis in general, other then here of course!!
 

Barnsley

Active member
Its not an area I am familiar with but for some reason I thought a processed wafer the price would be higher than that.
If these prices are so, then often the mask for a level could be a higher price than tje wafer for that level?
Is that correct?
 

Fred Chen

Moderator
Its not an area I am familiar with but for some reason I thought a processed wafer the price would be higher than that.
If these prices are so, then often the mask for a level could be a higher price than tje wafer for that level?
Is that correct?
Mask prices can be much higher, but they are amortized over many wafers of course.
 

IanD

Active member
Its not an area I am familiar with but for some reason I thought a processed wafer the price would be higher than that.
If these prices are so, then often the mask for a level could be a higher price than tje wafer for that level?
Is that correct?
Typical TSMC mask prices are in the same ballpark as the cost of 1000 wafers...
 

Fred Chen

Moderator
Thank you.

Was chatting about this to a customer earlier , the prices really surprise me especially at the low end ...
On the order of $500K for EUV, $100-200K for ArFi, $5000 for 14nm wafer.

I found one plot in the previously attached report interesting, where fewer wafers did not favor EUV at all (ArF multipatterning preferred).
 

Paul2

Active member
I get the impression that digitimes and trendforce regularly put out articles with rather dubious sourcing. Where is the place to look to find the latest on TSMC and semis in general, other then here of course!!

I have no doubt that Digitimes have sources on the ground, and far more than anybody in the industry news industry. I myself ran into their inquisitive journalists a few times.

The matter is that they are too inquisitive, and may put words into one's mouth because their boss is prone to "a lot thinking" and "big ideas".

Working in the industry you cannot not to read them, but you have to have skill to carve out a "kernel of truth" from their articles from accompanying speculative musings.

Also, their English version does a broken phone of their Chinese language coverage.
 

benb

Active member
This article gives you a ballpark price, maybe including the parking lot and local neighborhoods…

Here’s the thing. Smartphones demand is flat, PC demand is declining, graphics chip prices are sane again thanks to the crypto winter. I think it’s particularly hard to price wafers these days, even when you have a monopoly on 3nm as TSMC appears to have (de facto). It’s a game of covering your sunk costs without killing end demand too much. And end demand is killing itself, so it’s hard.

Maybe TSMC will consult with OPEC for advise about how to milk this cow without killing her.
 

MKWVentures

New member
I am not clear on what Daniel's take is on this article. TSMC wafer prices vary by volume and customer. 20K is not outrageous for a new node. If customers don't want this, then they can stay on old node or negotiate a better price. and the price will drop in the future, just like 10nm.

Side note: "using a 193nm immersion exposure machine with water as the medium to replace the traditional 157nm dry exposure. "
When was 157 Traditional? It was hypothetical.... wishful.... and then it disappeared.
 

Daniel Nenni

Admin
Staff member
I am not clear on what Daniel's take is on this article. TSMC wafer prices vary by volume and customer. 20K is not outrageous for a new node. If customers don't want this, then they can stay on old node or negotiate a better price. and the price will drop in the future, just like 10nm.

I don't care for articles that besmirch the semiconductor industry. $20k+ is not what companies in Silicon Valley are paying for N3 wafers. Think of the volumes Apple, Intel, AMD, NVIDIA, and QCOM are buying. And if you aren't buying high volumes of wafers you aren't buying N3.
 

Daniel Nenni

Admin
Staff member
"With TSMC's unit wafer prices for 3nm FINFET process topping US$20,000 and likely to rise further in 2023, Samsung Electronics may be able to obtain orders from major clients for its 3nm GAAFET process, according to Korean-language iNews 24."


In case you were wondering who would benefit from this fake news......
 
"With TSMC's unit wafer prices for 3nm FINFET process topping US$20,000 and likely to rise further in 2023, Samsung Electronics may be able to obtain orders from major clients for its 3nm GAAFET process, according to Korean-language iNews 24."


In case you were wondering who would benefit from this fake news......
Someone trying to manipulate on behalf of Samsung? Also digitimes just put out another poorly sourced article “asserting” that TSMC’s fab utilization rate is due to fall to just 80% in the first half of 2023. I find this extremely hard to believe. Has anyone heard this or is it just yet another Digitimes click bait piece. I swear the “semi conductor tabloids” just never rest with the rumour mill.

 
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Paul2

Active member
I don't care for articles that besmirch the semiconductor industry. $20k+ is not what companies in Silicon Valley are paying for N3 wafers. Think of the volumes Apple, Intel, AMD, NVIDIA, and QCOM are buying. And if you aren't buying high volumes of wafers you aren't buying N3.

It depends on what fab they made calculations for. If it was indeed that original 20k WPM 5nm fab in Arizona, then I would've said that it can be a realistic CPW in early productions. If Phoenix fab is 100k WPM+, then they should certainly hit a much lower cost than that.

This is why I was refusing to believe that Phoenix site is only 10-20k WPM, as that wouldn't make little sense economically even with huge subsidies. And it was totally not TSMC's style.
 

Tanj

Active member
Impact of mask costs on patterning strategy: https://www.euvlitho.com/2017/P33.pdf
Kasprowicz states:
Typical design is 11-Metal process with 66 masks
• @80% fab utilization mfg cost ~$4800 / 300mm wafer
• @ 1.3 layers / day, cycle time is ~90 days (min 3 months from start to delivery)

<I think that last calculation is upside down, should be 50 days start to delivery?>

Given that the FOUP carries 25 wafers which should take less than 10 minutes for all to pass through a litho machine, why does it take 18 hours per layer? Spin on resist is fast. Baking resist is a few minutes. Developing takes minutes. Etching and vapor or vacuum deposition should be minutes. Are any fabs organized for rapid turnaround, for example to build prototypes and pilots where hundreds of people may be idle until they can begin test and verification on the real thing? I'm aware that fabs are fabulous big scheduling problems but would be surprised to discover vast yards where FOUPs hang around doing nothing for hours...

What are the pain points for process latency? It is not the EUV machines...
 

nghanayem

Active member
Kasprowicz states:
Typical design is 11-Metal process with 66 masks
• @80% fab utilization mfg cost ~$4800 / 300mm wafer
• @ 1.3 layers / day, cycle time is ~90 days (min 3 months from start to delivery)

<I think that last calculation is upside down, should be 50 days start to delivery?>

Given that the FOUP carries 25 wafers which should take less than 10 minutes for all to pass through a litho machine, why does it take 18 hours per layer? Spin on resist is fast. Baking resist is a few minutes. Developing takes minutes. Etching and vapor or vacuum deposition should be minutes. Are any fabs organized for rapid turnaround, for example to build prototypes and pilots where hundreds of people may be idle until they can begin test and verification on the real thing? I'm aware that fabs are fabulous big scheduling problems but would be surprised to discover vast yards where FOUPs hang around doing nothing for hours...

What are the pain points for process latency? It is not the EUV machines...
From what I’ve seen wafers spend alot of time queued up on a tool (either docked to the tool or sitting in a storage robot with other foups), or waiting for the other wafers in a lot to process. Depending on the exact tool wafers could end up waiting a while for the wafer handling robots to move other wafers in/out of the process modules. The longest steps are often waiting for wafers to move in from EFEMs past load locks (kind of like an airlock and slow like one too) to get into the actual transfer units/process modules. At least for etchers wafers also need to outgas after processing.

The exact layer also can have a widely varying number of process steps. You might have to go from one etcher, to another, to an asher/clean tool. Then go to ald (depending on how much you are depositing this can be real slow), deposition, cmp (I think this is slow), and then back to litho. This gets even worse if that layer has any multi patterning.

As for high priority lots, that is a thing, and all fabs have them (as far as I know). However they are very disruptive to the fabs output/hurts wafer cost for the normal lots. For this reason foundries often charge extra for expedited lots. As far as I know development fabs do not have any special setup for high priority lots, just a higher volume of them. Depending on how much new equipment there is for that process impacts how negatively they effect factory output. When it is mostly new tools, then the priority lots don’t have to share with product lots, and cause minimal disruptions. Priority lots for prototypes, items of unexpectedly high demand that a customer is paying extra to expedite, or a new process that is using a large amount of current equipment has a larger impact on output.
 
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