These indicated 14nm (i.e., Samsung).
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These indicated 14nm (i.e., Samsung).
Too expensive. Anything 1m/year< will never leave 130nm-180nm because of lot sizes.
For most of mortals, a tapeout on 200mm is the only thing they can hope for in their lifetime.
Design of physical IP on immersion nodes is too expensive too. It's not what 10 years old pirated Cadence can do, nor what Indian, or Bangladeshi VHDL outsourcing shops specialise on.
The car companies really need to start designing out the old chips and designing in new ones like Tesla and the other emerging car companies. Learn the lesson of the business dinosaurs already: Innovate or Die.
Daniel, I respect your experience in the industry, but you keep saying that, and yet there are technical and economic reasons why 40nm+ nodes are still used throughout today's car. (And I'd be willing to bet this includes Tesla.) I am wondering which ICs you are referring to? All ICs in an automobile? Some large subset of them? Just the major ones?
I believe this for high-volume ICs that aren't low-cost. What kind of mask set costs (rough order of magnitude) are we talking about for 28nm?
IDK what the semiconductor companies need to justify producing a new IC in the $1-$2 range (high volume cost to customer) but I suspect the one-time costs for design and production need to be amortized over expected volume to be less than 20 cents*. (For required gross margin / operating margin, look at recent earnings reports.)
(*yes I work for a certain semiconductor manufacturer, no I do not work in IC design or production; this is a vague guess given that I don't want to find out a real number and deal with confidentiality constraints.)
Indeed, NOR flash on the microcontroller does not scale beyond 40nm foundry node (~60-70 nm active width). The high-k CMOS option of 28nm is a popular option (for a given cell size).The challenge has been eNVM on these nodes; 40nm eFlash qual for Auto was in 2018 (https://www.tsmc.com/english/dedicatedFoundry/technology/specialty/eflash), and the cycle time for auto components is ~3 years for the platform certification and then a ~10 year support lifetime commit from the manufacturer. So anyone that was designing a "new car" platform in 2019 would not have considered anything less than 40nm as appropriate if including eNVM. Renesas worked on porting their MONOS Flash to 28nm, and that was supposed to be ramping in 2020 (https://www.renesas.com/us/en/about...boration-next-generation-green-and-autonomous) - no idea if that panned out. N28/22 for Wireless / IoT applications with eNVM was focused on STT-MRAM or RRAM rather than eFlash, and the former has challenges with magnetics (so not going into any ECU), and the latter performance / endurance may not meet the spec of the part (incl temp range). If one were designing a new part in 2021/22 expected to launch in '24-'25 timeframe, then I would agree that 28nm is a good option, but their capacity is not limitless either - that's why they are expanding into Japan, to support the Sony ISP business.
Unrelated, but interesting was a paper from TSMC at VLSI in 2019 (I think) that showed their Wafer-on-Wafer attach putting a N40 die with eFlash atop an N16 logic die, specifically to bring that eNVM capability to a more advanced node, b/c the only current eNVMs for FinFET are still STT/SOT or RRAM based.
Will MPW (multi-project wafer) be possible and partially resolve the small lot size dilemmas?Too expensive. Anything 1m/year< will never leave 130nm-180nm because of lot sizes.
For most of mortals, a tapeout on 200mm is the only thing they can hope for in their lifetime.
Design of physical IP on immersion nodes is too expensive too. It's not what 10 years old pirated Cadence can do, nor what Indian, or Bangladeshi VHDL outsourcing shops specialise on.
Will MPW (multi-project wafer) be possible and partially resolve the small lot size dilemmas?
No, nobody will do this for real commercial use, especially for analog, where per-design process variation is needed. I doubt a 300mm MPW can be spun for non-academic, and non-test runs.
MPW is very inflexible for mainstream commercial use. Basically, you lose nearly all ability to say, when, and how much dies you want.
The challenge has been eNVM on these nodes; 40nm eFlash qual for Auto was in 2018 (https://www.tsmc.com/english/dedicatedFoundry/technology/specialty/eflash), and the cycle time for auto components is ~3 years for the platform certification and then a ~10 year support lifetime commit from the manufacturer. So anyone that was designing a "new car" platform in 2019 would not have considered anything less than 40nm as appropriate if including eNVM. Renesas worked on porting their MONOS Flash to 28nm, and that was supposed to be ramping in 2020 (https://www.renesas.com/us/en/about...boration-next-generation-green-and-autonomous) - no idea if that panned out. N28/22 for Wireless / IoT applications with eNVM was focused on STT-MRAM or RRAM rather than eFlash, and the former has challenges with magnetics (so not going into any ECU), and the latter performance / endurance may not meet the spec of the part (incl temp range). If one were designing a new part in 2021/22 expected to launch in '24-'25 timeframe, then I would agree that 28nm is a good option, but their capacity is not limitless either - that's why they are expanding into Japan, to support the Sony ISP business.
Unrelated, but interesting was a paper from TSMC at VLSI in 2019 (I think) that showed their Wafer-on-Wafer attach putting a N40 die with eFlash atop an N16 logic die, specifically to bring that eNVM capability to a more advanced node, b/c the only current eNVMs for FinFET are still STT/SOT or RRAM based.
Is there any other options available other than waiting for new fabs and additional fab capacity come online in two to three years to resolve the chip shortage?
A buddy of mine was working on exactly the same task: a cheap way to stack MCU dies with memory without TSVs, and expensive hybrid bonding, except doing it for SRAM instead of eFlash.
The idiocy of modern MCU design is that if you open a top-tier, fancy MCU on new nodes, you will find that 90% of the die is just huge eFLASH, and SRAM + tiny, tiny MCU core, and huge analog circuitry. So, on new nodes, actual core takes just few percents of the die space, and only these few percents of the area do get benefit from lower nodes. Everything else is negative value for the MCU.