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My questions is basically related to Metal width variation concepts.
Right now I have 2 question for you.
1) What are those factors (process) during the fabrication , which create the different biasing (width variation) on the basis of spacing with respect to neighboring metal wire. More clearly - for same wire width - but different wire spacing with other wires, biased values are different. Why from fabrication point of view.
2) We have different bias values for R and C. Like in ICT we have wee_c and wee_r ; in ITF we have ETCH_VS_WIDTH_AND_SPACING CAPACITIVE_ONLY | RESISTIVE_ONLY. How come a particular width biasing (or say change in the width value) only effect CAP or RES value ?
1) What are those factors (process) during the fabrication , which create the different biasing (width variation) on the basis of spacing with respect to neighboring metal wire. More clearly - for same wire width - but different wire spacing with other wires, biased values are different. Why from fabrication point of view.
2) We have different bias values for R and C. Like in ICT we have wee_c and wee_r ; in ITF we have ETCH_VS_WIDTH_AND_SPACING CAPACITIVE_ONLY | RESISTIVE_ONLY. How come a particular width biasing (or say change in the width value) only effect CAP or RES value ?
There are several contributors to R/C variations in interconnect. Some I can think about now:
1) For most/all of the current processes interconnects are made by first etching the lanes and then fill it up with the interconnect material. This filling is done in different steps which results in a material which in crosssection does not have uniform resistivity. This results in biases different for R and C as a function of width. The C is more determined by outer edge of interconnect, R by average resistivity.
2) Lithography is a 2D spatial low-pass filtering system. This means that the filltering depends on the frequency content of the pattern e.g. biasing will be different.
3) Etch also has density effects. Etching is done by bombarding loaded particles out of a plasma on the wafer surface under guidance of an electrical field. This field is not uniform but is (slightly) deformed by longer range density of the pattern and influencing etch speed. Additionally the etched away material may also influence local etching performance.
4) Planarization also has density effect. After trenches are filled with interconnect material (e.g. Cu) planarization is performed by so-called CMP (chemical-mechanical polishing). The filling is already dependent on density of the pattern. Additionally the polishing resistance is different between Cu and the dielectric also giving density effects and so called dishing and erosion. This can result in a thickness variation of the interconnect and thus have impact on R and C.
2) and 3) are mitigated by so-called optical proximity correction (OPC) by predistoring the pattern before printing to neutralize the filtering. This technique has it's limitation so something will finally remain. 4) and partly 3) are mitigated by dummy filling and pillars/holes put in large width interconnects.
Models you get in a PDK are a cumulation of all these effects and likely others. To pinpoint one phenomena as cause may difficult and can probably only be answered by a process expert. This one will only be accessible - if at all - if you order thousands of wafers. Mere mortals likely just have to trust the models provided.
