10 nm patterning at TSMC

[Fred Chen]

Semiconductor Engineering .:. The Bumpy Road To 10nm FinFETs

TSMC doing SAQP?

 

[IanD]

That's what's been said. Does anyone know what CPP and M1P they (or Intel, or Samsung) are using?

 

[khaki]

The VLSI'14 paper by IBM alliance (Samsung's engineer was actually lead author) quoted CPP=64nm (SADP), M1P=48nm (LELELE), MxP=45nm (SADP), FP=42nm (SADP). There is no need to SAQP with those numbers and I'd imagine TSMC numbers to be close.


Intel's starting point at 14nm is 70/52/42 nm for CPP/MxP/FP. A true 0.7X scaling will need 50/36/30nm. So, gate can continue with SADP, while metal and fin will need SAQP with multiple trim masks.

 

[Fred Chen]

I'd have used M1P of 44 nm to represent "10 nm" logic/foundry node. TSMC executives said this is too tight for LELELE, that may be why some have deduced SAQP (4 instead of 3). I think SADP probably would have sufficed for this M1P. Possibly the stronger reason to use SAQP is SADP at 10 nm would be one-time only while SAQP would allow them to follow up 10 nm more quickly with 7 nm (32 nm M1P) one year after (2017), since it uses the same flow.

 

[khaki]

With LELELE, 44nm pitch translates to 132nm pitch, which is in comfort zone of immersion litho for bidirectional features. Overlay will be a concern, but it gives so much freedom in local routing that justifies the burden. They can chose SADP for that if they accept unidirectional M1 and work out the standard cells with a combination of M1 and say local interconnect. But honestly using SAQP is overkill. Developing the process is one thing, converting a color-less design to SAQP features is totally different story. Assuming 10nm being a long life node, it does not make sense to insert features that are not needed - unnecessary cost and design complicity aside - just to practice them for the next node.

 

[IanD]

I agree that SAQP looks like overkill for 10nm, but the original article seemed pretty definite about TSMC using it. Does anyone know if this is confirmed from another source, or could it just be a misunderstanding/misreporting and TSMC will actually use SADP?

 

[Fred Chen]

Here is a quote from TSMC 2014 CSR, p. 17: http://www.tsmc.com/download/csr/2014_tsmc_csr/english/files/e_ch2.pdf

"..While the immersion lithography process will be extended to the 10nm node, the double patterning technique that was developed for the 20nm and 16nm nodes is insufficient to meet 10nm requirements. Multiple patterning becomes essential to enable high yield manufacturing. To further stretch the patterning capability of optical lithography, significant learning in material processing, image modeling, and defect control has been achieved to make the 10nm process viable."

On the page after: "..For the 10nm node and beyond, we have developed a new spacer-patterning scheme that allows copper line spacing to be reduced and minimizes signal delay."

 

[IanD]

Here is a quote from TSMC 2014 CSR, p. 17: http://www.tsmc.com/download/csr/2014_tsmc_csr/english/files/e_ch2.pdf

"..While the immersion lithography process will be extended to the 10nm node, the double patterning technique that was developed for the 20nm and 16nm nodes is insufficient to meet 10nm requirements. Multiple patterning becomes essential to enable high yield manufacturing. To further stretch the patterning capability of optical lithography, significant learning in material processing, image modeling, and defect control has been achieved to make the 10nm process viable."

On the page after: "..For the 10nm node and beyond, we have developed a new spacer-patterning scheme that allows copper line spacing to be reduced and minimizes signal delay."

So I would read that as "at 16nm and 20nm we use LELE DP, at 10nm and beyond we will use self-aligned spacer patterning" -- but it doesn't say if it's SADP or SAQP.

 

[Fred Chen]

I agree that SADP should be sufficient. Still the wording above could be different to remove all doubt. Like "a different double patterning technique" instead of "multiple patterning", or just "10nm node" without "and beyond".

 

[Portland]

I read that TSMC is collaborating with Intel on 10nm. TSMC wants to produce the excess demand outside of Kiryat Gat.

 

[IanD]

That would be a surprising move for TSMC, it would seem to be mainly to their disadvantage if the processes are compatible because it either gives Intel an SoC-targeted process to directly compete with TSMC for big-volume business like Apple, or it pushes TSMC more towards a CPU-targeted process which could put them at a disadvantage for the same business compared to Samsung.

All speculation anyway, everybody is keeping their 10nm cards under the table (at least in public) for obvious reasons...

 

[Staf_Verhaegen]

That would be a surprising move for TSMC

And if it would be true it's likely pushed by one of the big customers who likes to have second source.

 

[benb]

There is always a possibility Intel will go fab-lite. It makes more sense in a world where they can't maintain process leadership (that world probably arrives at 10nm). It depends on Intel's strategy going forward: If they want to diversify and be a foundry, then fab-lite wouldn't make sense. If they want to focus on being a chip designer for mature markets like PCs then fab-lite makes sense. Most developed-world semiconductor companies operating in mature markets have gone fab-lite.

 

[Fred Chen]

I just realized fin pitch was ignored. It will likely be below 40 nm for 10 nm node. It was 48 nm for TSMC's 16 nm node: TSMC Explains 16nm Process Technology; FinFET Introduced - Nikkei Technology Online. So projecting 33-34 nm (0.7x48) fin pitch at 10 nm node, that would be below the SADP resolution.