Unfortunately the 13 minute video from semitracks really glosses over the manufacturing process- and doesn't show how the transistors are made- nor does it show how the fins are actually patterned.
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Imagine a planar transistor. Fabrication process starts with forming STI regions that define the active regions (where will be later source/drain and channel region of the transistor). In planar transistor, after STI, well implants and Vt adjust implants are done, followed by gate stack formation (dummy gate in replacement gate flow), spacer, halo implant, extension, second spacer, deep S/D, ...
Now imaging, just after you form the STI you etch back a little bit of the STI oxide, so that the sidewalls of the active Si region are exposed. The gate stack will not only form on top of Si, but also on these sidewalls. In fact this a trick some beleive TSMC is playing in their recent 28HPC. It gives a little bit higher current for a given transistor layout.
Now, push the above trick further, make the active regions narrow (somewhere 10-20nm wide as opposed to typical 40-500 nm wide transistors in planar technology), and recess the STI a bit further (typically 30-40nm). You get a fin of Si. Once you form the gate, it wraps around this fin and you get an effective device width per fin equal to 2xfin height + fin width. For a fin height of 42nm, and fin width of 8nm (say Intel's 14nm node), you get an effective device width of 92nm per fin.
Next you need to pack the fins as close as possible. With immersion litho, you can place a fin every 80nm. That is a 92nm device width per 80nm of layout, which is a wash. That's where sidewall image transfer comes in to the picture, doubling the fin density. Both Intel and IBM used 42nm fin picth at 14-nm node (see upcoming IEDM). With a 92nm effective width, this gives you more than double the current you could get from a planar device, everything else kept same.
So, here is where finFET fabrication differs from planar CMOS:
1) define dense fins using sidewall image transfer. You'll need to do this twice if you need fin pitch less than 40nm (foundries 7nm most likely).
2) Etch these narrow and tall fins.
3) Fill the space between fins with oxide (this is comparable to STI in conventional CMOS, with the exception that the space is small).
4) Remove unwanted portions of fin. Immersion litho can remove every other fin if needed. But soon this will need double patterning and triple patterning as the device pitch is reduced in 10nm and beyond.
5) Recess the STI to expose sidewalls of fin. This (and any wet clean in the process) determines effective device width, and typical cross sections in fact show variation. So, don't expect all fins to give you exact same device width.
6) Well implant. Although similar to bulk planar in principle, in practice you need the dopants in the bottom portion of the fins only. That's a challenge.
7) Gate CMP. Since gate material is deposited on a surface with ~40nm topography, a polishing step is needed to make it planar.
8) Gate etch. Needs overetch to clean it from sidewalls of the fin in S/D.
9) Spacer etch. Need to etch it away from sidewall of the fin, but maintain it on gate sidewalls. Many beleived this was a driver for sloped fin sidewalls in Intel's 22nm. To make it easier to etch the spacer from fin sidewalls.
10) Junction formation. In planar transistor you need a shallow junction. In FinFET, junction needs to go all the way down the bottom of the fin and aligned to where the gate bottom is. Big challenge.
11) Strain engineering. BIG challenge. Strain engineering the way it worked from 90nm down to 32nm is dead. I have strong evidence for this.
12) Connectin fins together. In a pre-20nm node, you could plug a contact on a portion of S/D region. In FinFET, contact needs to connect all fins that belong to a given transistor together. This creats new design rules and wasted area.
The rest of the process is pretty much comparable to planar technology. Of course, there are small pieces here and there (like how to make passive devices), but I hope the above steps give a general feeling of where changes in the process are made.
