EU Chips Act 2.0 Webinar
OnlineEurope's Role & Chips Act 2.0 Priorities The European Union is currently developing a new version of the Chips Act program. The European Chips Act 2.0 represents a strategic initiative …
Europe's Role & Chips Act 2.0 Priorities The European Union is currently developing a new version of the Chips Act program. The European Chips Act 2.0 represents a strategic initiative …
*Work Email Required* Edge AI systems increasingly require on-chip integration of large-capacity memory, compute engines, and inference-optimized accelerators—all within strict power, latency, and footprint constraints. This webinar provides a an …
Continue reading "Webinar: IP Design Considerations for Real-Time Edge AI Systems"
The increasing demand for accelerated computing solutions calls for an agile hardware design methodology to be able to keep up with fast evolving landscape of algorithms. Traditional hardware design methodology …
As digital chip design complexity grows, engineering teams face increasing pressure to meet aggressive PPA targets on tight schedules. To overcome this challenge, the EDA industry requires a revolutionary shift …
Description BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. Unlock the potential of the AMD Kria SOM and discover Time-Sensitive Networking (TSN) benefits for …
October 29, 2025 - 11:00 AM EST October 30, 2025 – 10:00 AM JST/KST Discover the 5 Critical Memory Market Trends Reshaping Semiconductors in 2026 AI workloads, HBM4 adoption, and …
Continue reading "Webinar: 5 Expectations for the Memory Market in 2026"
Strengthen your knowledge and skills by learning about new packaging technologies in Fan-in, Fan-out WLP, Embedded packaging technology, System on Chip (SOC), System in Package (SiP), 3D IC, WLP, TSV, …
November 4, 2025 | 10:00 AM PST This webinar will present advanced simulation tools and techniques for the design of GaN power amplifiers with increased assurance of stable operation that …
Details Imaging radar has rapidly evolved into a critical technology for autonomous systems, with patent activity accelerating significantly over the past decade. From 2015 to 2024, global imaging radar patent …
High-Level Synthesis (HLS) is design flow in which design intent is described at a higher level of abstraction such as SystemC/C++/Matlab/etc. HLS tools are expected to synthesize this code to …
Continue reading "Webinar: HLV – Formal Verification of Synthesizable C++/SystemC Designs"
About this event Join Roger Nichols, 6G Program Manager, for an insightful discussion on the 6G spectrum. He will cover the current status of 6G technologies, standards, and policies for …
Join us for this engaging Master Class with Benyamin Davaji, PhD, Assistant Professor of Electrical and Computer Engineering at Northeastern University and Peter Doerschuk, Professor of Electrical and Computer Engineering and Biomedical Engineering at Cornell University, as they explore the role of digital twin models in advancing semiconductor manufacturing. The masterclass will highlight how data-guided …