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Featured Speaker: Victoria Kolesov, Principal Engineer, Intel In this Synopsys webinar, Intel will present how its disaggregated designs across client and server platforms have driven the evolution of robust 3D multi-die design construction and signoff methodologies. Intel will share practical experience using Synopsys’ complete design implementation and signoff flows for static timing analysis signoff and …
AI data center networks now operate at a scale where device-level validation no longer reflects real performance. Engineers must understand how systems behave under realistic traffic conditions, not just in isolated tests. Join Ram Periakaruppan, vice president and general manager of network applications and security at Keysight, to learn how large-scale traffic emulation reveals congestion, …
As 5G and future 6G networks increase RF front-end complexity, acoustic wave filters and RF front-end modules are facing growing demands for higher frequency operation, wider bandwidth, lower losses, better thermal stability and deeper integration. Based on KnowMade’s latest analyses of RF Acoustic Wave Filters and RF Front-End Modules & Components, this seminar will explore how patent activity up …
*Company Email Required for Registration* Full-chip SoC debug has become one of the most expensive bottlenecks in modern verification. A single production issue can pull multiple engineers away days as they chase a failure through waveforms, logs, and across hundreds of thousands of lines of code. In this webinar, we will demonstrate how the Bronco …
As semiconductor complexity increases and board designs become denser, manufacturing teams face tighter tolerances, reduced test access, and rising pressure to maintain yield and throughput. Validating RF performance and high-speed digital signal integrity at production scale adds a new layer of complexity that traditional approaches struggle to address. Join Jason Kary, Senior Vice President and …
In this webinar with eShard, we dive into one of the most pressing questions in the community: Are physical attacks practical against post-quantum schemes in the real world? If yes, how to harden the code or the hardware? We’ll explore: How can cryptographic algorithms and their implementations be targeted by physical attacks? Leveraging a novel …
About this event This presentation provides a high‑level overview of how the updates in the 2026 Keysight Optical Design Engineering (ODE) product releases address emerging application areas, such as AR/VR systems, metamaterials, imaging and illumination design, and the evolving roadmap toward a unified platform for photonic integrated circuit (PIC) design. Updates featured come from CODE …
About this event Engineering at the Edge Webinar Series - Episode 2 As systems move into higher frequencies and wider bandwidths, small measurement errors can lead to costly design decisions. Engineers working in wireless, radar, satellite, and optical domains must now validate signals that push existing tools to their limits. Join Jun Chie, Vice President of Product …
**Work Email Required for Registration** Embedded systems programs rarely fail because any one team lacks capability. They fail because critical engineering artifacts drift out of alignment over time and distance. This includes requirements, architecture, implementation, verification, hardware bring-up, firmware, and customer documentation. Local correctness does not guarantee lifecycle coherence. llmda.ai believes that consistency itself should …
About this event The Inference Stack Can Talk. Learn How to Listen. AI has entered the inference era. For years the industry focused on training models. But today the real challenge is running AI workloads in production at scale. In this webinar, you’ll have the opportunity to learn how to decode the signals from your inference stack and turn them into smarter infrastructure …
About this event This webinar showcases how the Keysight Technologies SOS extension integrates design data management directly into Visual Studio Code, helping digital design and verification teams streamline RTL and HDL workflows without leaving their coding environment. Who should attend this event? Digital design engineers writing RTL in SystemVerilog, Verilog, or VHDL who use VS Code …
About this event This webinar shows how engineers can use a unified EOE simulation workflow in Keysight Advanced Design System (ADS) to co-design and validate high-speed Ethernet systems across both electronic and photonic domains for faster, more accurate development. Who should attend this event? Signal integrity engineers working on high-speed Ethernet links, Photonic design engineers …
