Hardware security is essential for high-performance computing (HPC), AI, and Edge IoT applications when designing SoCs in advanced process nodes. These designs include Gigabits of SRAM and require storing >16Kb of repair information to meet yield requirements. Designers are facing the challenges of creating secure, reliable, and cost-effective SoC designs in a timely manner. If …
Join us for an insightful presentation into the integration of Synopsys Verdi® and Euclide IDE, revolutionizing the debugging landscape for hardware designers. In this session, we’ll delve into next-generation Verdi’s integration with Euclide IDE, a cutting-edge integrated development environment. Discover how Euclide IDE empowers designers to find bugs earlier and optimize code for design and …
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The adoption of wide-bandgap power MOSFETs (SiC and GaN) is growing in power electronic applications for consumer electronics, automotive, and renewable energy. Successful implementation of simulation in system design requires high-fidelity, numerically robust, and compact power MOSFET models. The Saber circuit simulation environment offers a proven and mature solution with a dedicated tool that allows …
In recent years, the semiconductor industry has experienced a breakthrough in the onset of 2.5D and 3D chiplet-based products. These products promise to extend the limits of Moore’s Law while demolishing limitations on speed and capacity for our highest tiers of compute. But for all the adulation we heap upon the 3DIC paradigm, we seemingly …
ASIP Designer enables the creation of custom vector DSPs for AI Wednesday, May 22, 2024 4:00 - 6:00 pm CEST / 7:00 - 9:00 am PT Case Studies accelerating AI …
Synopsys' SLM PVT Monitor (process detector, voltage monitor, temperature sensor) IP can collect voltage, temperature, and process parameters from different blocks within the IC in real time. These data can be analyzed and used to take meaningful action to optimize the performance of the chip at any stage of silicon lifecycle. This webinar focuses on …
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Thursday, May 30, 2024 | 10:00-11:00 a.m. PDT Many automotive applications require processing workloads with minimum latency and precise timing budgets. This is especially true for safety-critical applications like adaptive cruise control and anti-lock braking, where human life may be jeopardized. These systems require processing elements that can respond to events within specific (predictable) time …
Today’s advanced node chip designs are faced with many new complexities which require more verification, more validation and more analysis. The resulting data from these added steps has also grown …
Join us at Virtual Prototyping Day 2024 to hear about the latest deployed virtual prototyping innovations. This event highlights applications from around the world using the latest virtual prototyping technology, …
Today, we find ourselves at the nexus of the fourth industrial revolution — an era dominated by Smart Everything. The internet, artificial intelligence, and the use of software are helping to create things that couldn’t even be imagined just a decade or two ago. The opportunities seem limitless, and the potential for more world-changing technologies …
The digital chip design flow carries with it an enormous wealth of untapped information regarding the health and status of your SoC design. The ability to efficiently mine this data provides chip designers with comprehensive visibility and actionable insights to uncover PPA opportunities. This webinar will introduce you to Synopsys Design.da, the industry’s first comprehensive data-visibility …
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Leveraging functional patterns is crucial for achieving high defect coverage and reducing defective parts per million (DPPM) levels. Synopsys VC Z01X fault simulator offers enhanced fault coverage in manufacturing test flows, complementing ATPG tools like Synopsys TestMAX ATPG. In this presentation we will delve into unique coverage scenarios, such as resets and clocks blocked during ATPG mode. We'll …
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