As hyperscaler chiplet and SoCs grow in complexity, integrating and validating multiple high-speed and low-speed interface protocols—such as PCIe, CXL, UCIe, AMBA, AXI, AHB, CHI, CSI2, and DSI2, can be a significant challenge. Design Verification Engineers and Technical Managers must ensure seamless protocol compliance while staying focused on their core ASIC design value. Join us …
As hyperscaler chiplet and SoCs grow in complexity, integrating and validating multiple high-speed and low-speed interface protocols—such as PCIe, CXL, UCIe, AMBA, AXI, AHB, CHI, CSI2, and DSI2, can be a significant challenge. Design Verification Engineers and Technical Managers must ensure seamless protocol compliance while staying focused on their core ASIC design value. Join us …
Software Defines Everything For today’s SoC and system designs, hardware is designed and optimized for the software workload. Workloads can include firmware, multi-OS architectures, AI/ML and complex graphics. These combined produce large software models that put pressure on system-level verification. What is the Arm Compute Subsystem (CSS) A compute subsystem is a pre-integrated, optimized …
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Join us in Munich where peer-delivered technical sessions will be shared across a breadth of topics so you can explore new concepts or dive deep in your core area of expertise with fellow like-minded professionals. Munich, Germany | May 13, 2025 Registration opens Feb. 10, 2025. About User2User The User2User conference is your opportunity to …
Join us for the User2User North America event, which is a dedicated environment for exchanging ideas, information, and best practices that enable you to lead in your role and achieve success with your customers. Santa Clara, CA | Santa Clara Marriott May 20, 2025 Registration opens Feb. 10, 2025. About User2User The User2User event is …
Wednesday, May 21 - 8:00 AM Pacific The semiconductor industry faces a critical Verification Productivity Gap 2.0, driven by increasingly complex technologies including 3DICs, chiplet-based designs, and software-defined architectures. This challenge is compounded by demands for Enhanced security, Reduced power consumption, Improved reliability, Greater sustainability and Talent shortage mitigation. Traditional verification methods, including constrained-random and …
Wednesday, May 28 - 8:00 AM Pacific Managing traceability across multiple disconnected tools and data is a challenge that often leads to inefficiencies, missed coverage, and increased risk in safety-critical designs. In this webinar, discover how Questa Verification IQ Testplan Author seamlessly integrates with Application Lifecycle Management tools (such as Siemens Polarion and Jama Connect) …
Join our community of thinkers and doers in design, manufacturing, and lifecycle management to accelerate your digital transformation. Detroit, Michigan | June 2-5, 2025 Registration opens Jan. 14, 2025. Where your digital transformation gets real. Fast. Join our community of thinkers and doers in design, manufacturing, and lifecycle management to accelerate your digital transformation. Relive …
Wednesday, June 4 - 8:00 AM Pacific In today's automotive electronics, ensuring functional safety is paramount for meeting stringent industry standards. This webinar introduces Questa One Sim FX, a cutting-edge fault simulation platform designed specifically for complex automotive designs. We'll explore how this high-performance tool revolutionizes the safety verification process through intelligent fault injection at …
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Rising semiconductor complexity—driven by multi-die architectures, the move towards more advanced technology nodes, and more stringent reliability targets, is dramatically increasing the volume of verification required to achieve DFT verification sign-off. Come learn how the Questa One DFT Verification solution, combined with Tessent Silicon Lifecycle Solutions delivers an evolution in user experience and performance to …
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This webinar introduces Questa One Sim CX, an innovative coverage-driven simulation solution that revolutionizes SystemVerilog UVM verification workflows. Traditional coverage closure methods, relying on constrained-random stimulus generation and iterative manual adjustments, often prove time-consuming and resource-intensive. Questa One Sim CX addresses these challenges by automatically inferring relationships between functional coverage bins and randomized stimulus variables, …
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About This Webinar Are you ready to disrupt decades of outdated processes and lead a smarter, more sustainable future in semiconductor manufacturing? While the digital twin has long been a cornerstone of chip design, its power has yet to be fully harnessed on the fab floor. Meanwhile, manufacturers experience increased pressure from rising costs, slow …
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June 24, 2025 12:00 PM -1:00 PM Moscone West | San Francisco, CA Calibre: Supercharge your chip integration efforts Siemens is excited to host an exclusive event for our customers at the Design Automation Conference Join us at DAC for lunch and learn how our new products can supercharge your chip integration efforts: - Chip …
