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CadenceTECHTALK: High Performance Hierarchical IR Signoff for Large SoCs and 3D-ICs
CadenceTECHTALK: High Performance Hierarchical IR Signoff for Large SoCs and 3D-ICs
Webinar Details IR signoff for advanced SoCs and 3D-ICs is a major challenge due to extremely large and complex power networks that can exceed 100 billion nodes. Designers are faced with very long runtimes and very large compute resource requirements amounting to thousands of CPUs and 100TB+ memory to run a full-chip flat. In this …